Patents by Inventor Ryuichi Mishima
Ryuichi Mishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8163588Abstract: A manufacturing method of a photoelectric conversion device included a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second conductivity type, which is the opposite conductivity type to the first conductivity type, by implanting ions in the semiconductor region using the gate electrode of the transfer transistor and a portion covering a side face of the gate electrode of the transfer transistor of the insulation film as a mask in a state in which the semiconductor substrate and the gate electrode of the transfer transistor are covered by the insulation film, and causing a portion of the semiconductor region of the first conductivity type from which the protection region is removed to be the charge accumulation region.Type: GrantFiled: March 28, 2011Date of Patent: April 24, 2012Assignee: Canon Kabushiki KaishaInventors: Ryuichi Mishima, Mineo Shimotsusa, Hiroaki Naruse
-
Publication number: 20110254065Abstract: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V).Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Hiroshi Yuzurihara, Seiichi Tamura, Ryuichi Mishima
-
Publication number: 20110244627Abstract: In a method of manufacturing a photoelectric conversion device having a pixel region and a peripheral circuit region, a semiconductor compound layer is formed by causing a surface of a diffusion layer or gate electrode of a MOS transistor in the peripheral circuit region to react with a high melting point metal, then an insulating layer is formed in the pixel region and the peripheral circuit region after the step of forming a semiconductor compound layer. A contact hole is formed in the insulating layer to expose a diffusion layer in the pixel region, and a contact hole is formed in the insulating layer to expose the semiconductor compound layer formed in the peripheral circuit region. These holes are formed at different timings. Prior to forming the hole which is formed later, a contact plug is formed in the contact hole which is formed earlier.Type: ApplicationFiled: June 16, 2011Publication date: October 6, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Takehito Okabe, Hiroaki Naruse, Ryuichi Mishima, Kouhei Hashimoto
-
Patent number: 7994552Abstract: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V).Type: GrantFiled: March 4, 2008Date of Patent: August 9, 2011Assignee: Canon Kabushiki KaishaInventors: Hiroshi Yuzurihara, Seiichi Tamura, Ryuichi Mishima
-
Patent number: 7993951Abstract: In a method of manufacturing a photoelectric conversion device having a pixel region and a peripheral circuit region, a semiconductor compound layer is formed by causing a surface of a diffusion layer or gate electrode of a MOS transistor in the peripheral circuit region to react with a high melting point metal, then an insulating layer is formed in the pixel region and the peripheral circuit region after the step of forming a semiconductor compound layer. A contact hole is formed in the insulating layer to expose a diffusion layer in the pixel region, and a contact hole is formed in the insulating layer to expose the semiconductor compound layer formed in the peripheral circuit region. These holes are formed at different timings. Prior to forming the hole which is formed later, a contact plug is formed in the contact hole which is formed earlier.Type: GrantFiled: June 3, 2010Date of Patent: August 9, 2011Assignee: Canon Kabushiki KaishaInventors: Takehito Okabe, Hiroaki Naruse, Ryuichi Mishima, Kouhei Hashimoto
-
Publication number: 20110171770Abstract: A manufacturing method of a photoelectric conversion device included a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second conductivity type, which is the opposite conductivity type to the first conductivity type, by implanting ions in the semiconductor region using the gate electrode of the transfer transistor and a portion covering a side face of the gate electrode of the transfer transistor of the insulation film as a mask in a state in which the semiconductor substrate and the gate electrode of the transfer transistor are covered by the insulation film, and causing a portion of the semiconductor region of the first conductivity type from which the protection region is removed to be the charge accumulation region.Type: ApplicationFiled: March 28, 2011Publication date: July 14, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Ryuichi Mishima, Mineo Shimotsusa, Hiroaki Naruse
-
Patent number: 7977760Abstract: A manufacturing method is provided for a photoelectric conversion device in which no plane channeling is produced. The photoelectric conversion device includes a silicon substrate and a photoelectric conversion element on one principal plane of the silicon substrate that forms an off-angle ? with at least two planes perpendicular to a reference (1 0 0) plane within a range of 3.5°???4.5°, and an ion injecting direction for forming a semiconductor region constituting the photoelectric conversion element forms an angle ? to a direction perpendicular to the principal plane within a range of 0°<??45°, and further a direction of a projection of the ion injecting direction to the principal plane forms each angle ? with the two plane direction within a range of 0°<?<90°.Type: GrantFiled: May 5, 2009Date of Patent: July 12, 2011Assignee: Canon Kabushiki KaishaInventors: Seiichi Tamura, Hiroshi Yuzurihara, Shigeru Nishimura, Ryuichi Mishima, Yasushi Nakata
-
Publication number: 20110163407Abstract: A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C1 corresponding to a peak of the impurity concentration in the first impurity region, a concentration C2 corresponding to a peak of the impurity concentration in the second impurity region and a concentration C3 corresponding to a peak of the impurity concentration in the third impurity region satisfy the following relationship: C2<C3<C1.Type: ApplicationFiled: March 16, 2011Publication date: July 7, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Hiroshi YUZURIHARA, Ryuichi MISHIMA, Takanori WATANABE, Takeshi ICHIKAWA, Seiichi TAMURA
-
Patent number: 7935557Abstract: A manufacturing method of a photoelectric conversion device included a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second conductivity type, which is the opposite conductivity type to the first conductivity type, by implanting ions in the semiconductor region using the gate electrode of the transfer transistor and a portion covering a side face of the gate electrode of the transfer transistor of the insulation film as a mask in a state in which the semiconductor substrate and the gate electrode of the transfer transistor are covered by the insulation film, and causing a portion of the semiconductor region of the first conductivity type from which the protection region is removed to be the charge accumulation region.Type: GrantFiled: November 20, 2009Date of Patent: May 3, 2011Assignee: Canon Kabushiki KaishaInventors: Ryuichi Mishima, Mineo Shimotsusa, Hiroaki Naruse
-
Patent number: 7928486Abstract: A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C1 corresponding to a peak of the impurity concentration in the first impurity region, a concentration C2 corresponding to a peak of the impurity concentration in the second impurity region and a concentration C3 corresponding to a peak of the impurity concentration in the third impurity region satisfy the following relationship: C2<C3<C1.Type: GrantFiled: December 18, 2009Date of Patent: April 19, 2011Assignee: Canon Kabushiki KaishaInventors: Hiroshi Yuzurihara, Ryuichi Mishima, Takanori Watanabe, Takeshi Ichikawa, Seiichi Tamura
-
Publication number: 20110049332Abstract: A photoelectric conversion device having a pixel array region in which a plurality of pixels each including a photoelectric converter are arrayed, and a peripheral region arranged around the pixel array region, the device comprising a multilayer wiring structure which is arranged on a semiconductor substrate, and includes wiring layers in the peripheral region more than wiring layers in the pixel array region, and a plurality of interlayer lenses which is arranged on the multilayer wiring structure in the pixel array region, wherein the plurality of interlayer lenses each includes a first insulator, and a second insulator arranged to cover the first insulator, and having a refractive index higher than the first insulator, and wherein the first insulator in each of the plurality of interlayer lenses, and an uppermost interlayer insulating film in the peripheral region in the multilayer wiring structure are made of an identical material.Type: ApplicationFiled: August 10, 2010Publication date: March 3, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Hiroaki Naruse, Ryuichi Mishima
-
Publication number: 20110027934Abstract: A photoelectric conversion apparatus includes: a first interlayer insulation film disposed on a semiconductor substrate; a first plug disposed in a first hole in the first interlayer insulation film, and serving to electrically connect between a plurality of active regions disposed in the semiconductor substrate, between gate electrodes of a plurality of MOS transistors, or between the active region and the gate electrode of the MOS transistor, not through the wiring of the wiring layer; and a second plug disposed in a second hole in the first interlayer insulation film, the second plug being electrically connected to the active region, wherein a wiring arranged over the second plug and closest to the second plug is electrically connected to the second plug, and the wiring electrically connected to the second plug forms a portion of dual damascene structure. By such a structure, incidence efficiency of light onto a photoelectric conversion element can be improved.Type: ApplicationFiled: October 14, 2010Publication date: February 3, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Hiroaki Naruse, Takashi Okagawa, Ryuichi Mishima, Nobuhiko Sato, Hiroshi Yuzurihara
-
Publication number: 20100330723Abstract: In a method of manufacturing a photoelectric conversion device having a pixel region and a peripheral circuit region, a semiconductor compound layer is formed by causing a surface of a diffusion layer or gate electrode of a MOS transistor in the peripheral circuit region to react with a high melting point metal, then an insulating layer is formed in the pixel region and the peripheral circuit region after the step of forming a semiconductor compound layer. A contact hole is formed in the insulating layer to expose a diffusion layer in the pixel region, and a contact hole is formed in the insulating layer to expose the semiconductor compound layer formed in the peripheral circuit region. These holes are formed at different timings. Prior to forming the hole which is formed later, a contact plug is formed in the contact hole which is formed earlier.Type: ApplicationFiled: June 3, 2010Publication date: December 30, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Takehito Okabe, Hiroaki Naruse, Ryuichi Mishima, Kouhei Hashimoto
-
Patent number: 7838918Abstract: A photoelectric conversion apparatus includes: a first interlayer insulation film disposed on a semiconductor substrate; a first plug disposed in a first hole in the first interlayer insulation film, and serving to electrically connect between a plurality of active regions disposed in the semiconductor substrate, between gate electrodes of a plurality of MOS transistors, or between the active region and the gate electrode of the MOS transistor, not through the wiring of the wiring layer; and a second plug disposed in a second hole in the first interlayer insulation film, the second plug being electrically connected to the active region, wherein a wiring arranged over the second plug and closest to the second plug is electrically connected to the second plug, and the wiring electrically connected to the second plug forms a portion of dual damascene structure. By such a structure, incidence efficiency of light onto a photoelectric conversion element can be improved.Type: GrantFiled: February 6, 2008Date of Patent: November 23, 2010Assignee: Canon Kabushiki KaishaInventors: Hiroaki Naruse, Takashi Okagawa, Ryuichi Mishima, Nobuhiko Sato, Hiroshi Yuzurihara
-
Publication number: 20100219497Abstract: The present invention, in a photoelectric conversion device in which a pixel including a photoelectric conversion device for converting a light into a signal charge and a peripheral circuit including a circuit for processing the signal charge outside a pixel region in which the pixel are disposed on the same substrate, comprising: a first semiconductor region of a first conductivity type for forming the photoelectric region, the first semiconductor region being formed in a second semiconductor region of a second conductivity type; and a third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type for forming the peripheral circuit, the third and fourth semiconductor regions being formed in the second semiconductor region; wherein in that the impurity concentration of the first semiconductor region is higher than the impurity concentration of the third semiconductor region.Type: ApplicationFiled: May 13, 2010Publication date: September 2, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Seiichi Tamura, Hiroshi Yuzurihara, Takeshi Ichikawa, Ryuichi Mishima
-
Publication number: 20100221864Abstract: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.Type: ApplicationFiled: May 14, 2010Publication date: September 2, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Toru Koizumi, Akira Okita, Tetsuya Itano, Sakae Hashimoto, Ryuichi Mishima
-
Publication number: 20100173444Abstract: A manufacturing method of a photoelectric conversion device comprises a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second conductivity type, which is the opposite conductivity type to the first conductivity type, by implanting ions in the semiconductor region using the gate electrode of the transfer transistor and a portion covering a side face of the gate electrode of the transfer transistor of the insulation film as a mask in a state in which the semiconductor substrate and the gate electrode of the transfer transistor are covered by the insulation film, and causing a portion of the semiconductor region of the first conductivity type from which the protection region is removed to be the charge accumulation region.Type: ApplicationFiled: November 20, 2009Publication date: July 8, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Ryuichi Mishima, Mineo Shimotsusa, Hiroaki Naruse
-
Patent number: 7745247Abstract: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.Type: GrantFiled: October 13, 2008Date of Patent: June 29, 2010Assignee: Canon Kabushiki KaishaInventors: Toru Koizumi, Akira Okita, Tetsuya Itano, Sakae Hashimoto, Ryuichi Mishima
-
Patent number: 7737519Abstract: The present invention, in a photoelectric conversion device in which a pixel including a photoelectric conversion device for converting a light into a signal charge and a peripheral circuit including a circuit for processing the signal charge outside a pixel region in which the pixel are disposed on the same substrate, comprising: a first semiconductor region of a first conductivity type for forming the photoelectric region, the first semiconductor region being formed in a second semiconductor region of a second conductivity type; and a third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type for forming the peripheral circuit, the third and fourth semiconductor regions being formed in the second semiconductor region; wherein in that the impurity concentration of the first semiconductor region is higher than the impurity concentration of the third semiconductor region.Type: GrantFiled: April 27, 2005Date of Patent: June 15, 2010Assignee: Canon Kabushiki KaishaInventors: Seiichi Tamura, Hiroshi Yuzurihara, Takeshi Ichikawa, Ryuichi Mishima
-
Publication number: 20100096676Abstract: A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C1 corresponding to a peak of the impurity concentration in the first impurity region, a concentration C2 corresponding to a peak of the impurity concentration in the second impurity region and a concentration C3 corresponding to a peak of the impurity concentration in the third impurity region satisfy the following relationship: C2<C3<Cl.Type: ApplicationFiled: December 18, 2009Publication date: April 22, 2010Applicant: Cannon Kabushiki KaishaInventors: Hiroshi YUZURIHARA, Ryuichi MISHIMA, Takanori WATANABE, Takeshi ICHIKAWA, Seiichi TAMURA