Abstract: A controlling section causes a charge of a photodiode to be output to an integration circuit by bringing a readout switch into a connected state, and then brings the readout switch into a non-connected state. Thereafter, a voltage value is output to a holding circuit from the integration circuit. After carrying out the output operation mentioned above, an operation for causing a charge held in an integrating capacitive element to be discharged, and bringing the readout switch into a connected state to cause a charge held in the photodiode to be discharged and an operation for causing voltage values held in the holding circuits to be sequentially output are carried out in parallel. Accordingly, a solid-state imaging device and a method of driving it capable of solving the problems due to a memory effect, a delay effect, and switching noise are realized.

Abstract: A solid-state imaging device includes a photodetecting section including pixels each including a transistor and a photodiode, readout wiring lines connected to the transistors, a signal output section for sequentially outputting voltage values according to the amounts of charges input through the respective readout wiring lines, potential change switches for switching the potentials of the readout wiring lines to a potential Vdr different from input potentials of integration circuits of the signal output section, and a controlling section. The controlling section switches potentials of the readout wiring lines to the different potential Vdr for a predetermined period included in a period, after an elapse of a readout period where voltage values corresponding to the amounts of charges generated in the pixels are sequentially output from the signal output section, until a next readout period is started.

Abstract: A solid-state image pickup apparatus 1A includes a photodetecting section 10A and a signal readout section 20 etc. In the photodetecting section 10A, M×N pixel units P1,1 to PM,N are arrayed in M rows and N columns. When in a first imaging mode, a voltage value according to an amount of charges generated in a photodiode of each of the M×N pixel units in the photodetecting section 10A is output from the signal readout section 20. When in a second imaging mode, a voltage value according to an amount of charges generated in the photodiode of each pixel unit included in consecutive M1 rows in the photodetecting section 10A is output from the signal readout section 20. When in the second imaging mode than when in the first imaging mode, the readout pixel pitch in frame data is smaller, the frame rate is higher, and the gain being a ratio of an output voltage value to an input charge amount in the signal readout section 20 is greater.

Abstract: A vertical shift register section includes M logic circuits for outputting row selection control signals respectively to M row selection wiring lines and shift register circuits disposed for every two row selection wiring lines. The M logic circuits, when a binning control signal Vbin1 or Vbin2 and an output signal of the shift register circuit both have significant values, output a row selection control signal Vsel so as to close a readout switch. The vertical shift register section, by controlling the timing at which the binning control signals Vbin1 and Vbin2 take significant values, realizes a normal operation mode for successively selecting the two row selection wiring lines and a binning operation mode for simultaneously selecting the two row selection wiring lines. Accordingly, a vertical binning operation is realized by a small vertical shift register.

Abstract: A controlling section, by bringing readout switches of pixels of a certain row out of the M rows into a connected state, causes charges generated in the row to be input to integration circuits, causes first holding circuits to hold voltage values output from the integration circuits, and then brings transfer switches into a connected state to transfer the voltage values to the second holding circuits, and thereafter performs in parallel an operation for causing the voltage values to be sequentially output from the second holding circuits and an operation for, by bringing readout switches of pixels of another row into a connected state, causing charges generated in the row to be input to the integration circuits. Accordingly, a solid-state imaging device and a driving method thereof capable of suppressing variations in output characteristics, while solving the problem due to a delay effect are realized.

Abstract: The present invention relates to a solid-state imaging device, etc. having a structure for capturing a high-resolution image even when any row selecting wiring is disconnected. The solid-state imaging device (1) comprises a photodetecting section (10), a signal reading-out section (20), a row selecting section (30), a column selecting section (40), an overflow preventing section (50), and a controlling section (60). The photodetecting section (10) has M×N pixel portions P1,1 to PM,N two-dimensionally arranged in a matrix of M rows and N columns, and each of the pixel portions P1,1 to PM,N includes a photodiode that generates charge of an amount according to an incident light intensity and a reading-out switch connected to the photodiode. Each of the N pixel portions Pm,1 to Pm,N belonging to an m-th row is connected to the row selecting section (30) and the overflow preventing section (50) by an m-th row selecting wiring LV,m.

Abstract: The present invention relates to a solid-state imaging device and the like having a structure for capturing a high-resolution image even when any of the reading-out wiring and row selecting wiring is disconnected. The solid-state imaging device (1) comprises a photodetecting section (10) having M×N pixel portions P1,1 to PM,N two-dimensionally arranged in a matrix of M rows and N columns. A pixel portion Pm,n of the photodetecting section (10) includes a photodiode PD generating charge of an amount according to an incident light intensity and a reading-out switch SW1 connected to the photodiode PD. The pixel portion Pm,n occupies a substantially square region, and most of the region is a region of the photodiode PD. A field-effect transistor serving as the reading-out switch SW1 is formed in one corner of the region. A channel stopper CS is continuously formed in a region sandwiched by pixel portions.

Abstract: The present invention relates to a solid-state imaging device, etc., having a structure which enables to obtain an image with higher resolution by correcting pixel data even when any one of row selecting wirings is disconnected. A solid-state imaging device (1) comprises a photodetecting section (10), a signal reading-out section (20), a controlling section (30), and a correction processing section (40). The photodetecting section (10) has M×N pixel portions P1,1 to PM,N two-dimensionally arrayed in M rows and N columns, and each of the pixel portions P1,1 to PM,N includes a photodiode which generates charges of an amount corresponding to an incident light intensity and a reading-out switch connected to the photodiode. Charges generated in each of the pixel portions P1,1 to PM,N are inputted into an integrating circuit Sn through a reading-out wiring LO,n.

Abstract: The present invention relates to a solid-state imaging device and the like having a structure for capturing a high-resolution image even when any of the reading-out wiring and row selecting wiring is disconnected. A pixel portion Pm,n of the photodetecting section (10) includes a photodiode PD generating charge of an amount according to an incident light intensity and a reading-out switch SW1 connected to the photodiode PD. The pixel portion Pm,n occupies a substantially square region, and most of the region is a region of the photodiode PD. A field-effect transistor serving as the reading-out switch SW1 is formed in one corner of the region. A channel stopper CS is continuously formed in a region sandwiched by pixel portions. In a region surrounded by any 2×2 pixel portions adjacent to one another, a dummy photodiode PD1 surrounded by the channel stopper CS is formed.

Abstract: The present invention relates to a solid-state imaging device, etc. having a structure for capturing a high-resolution image even when any row selecting wiring is disconnected. The solid-state imaging device (1) comprises a photodetecting section (10), a signal reading-out section (20), a row selecting section (30), a column selecting section (40), an overflow preventing section (50), and a controlling section (60). The photodetecting section (10) has M×N pixel portions P1,1 to PM,N two-dimensionally arranged in a matrix of M rows and N columns, and each of the pixel portions P1,1 to PM,N includes a photodiode that generates charge of an amount according to an incident light intensity and a reading-out switch connected to the photodiode. Each of the N pixel portions Pm,1 to Pm,N belonging to an m-th row is connected to the row selecting section (30) and the overflow preventing section (50) by an m-th row selecting wiring LV,m.

Abstract: For a solid-state image pickup device 1, a plurality of pixels are two dimensionally arranged in an imaging region 10, and two photodiodes PD1 and PD2 are included in each pixel Pm,n. An electric charge generated in the respective photodiodes PD1 and PD2 is input to a signal readout section 20, and a voltage according to an electric charge amount thereof is output from the signal output section 20. The voltage output from the signal readout section 20 is input to an A/D converting section 40, and a digital value according to the input voltage is output from the A/D converting section 40. In an adding section 50, a sum of digital values to be output from the A/D converting section 40 according to the amount of electric charge generated, for each pixel Pm,n of the imaging region 10, in the two respective photodiodes PD1 and PD2 included in the pixel is operated, and a digital value being a sum value thereof is output.

Abstract: A solid-state image pickup apparatus 1A includes a photodetecting section 10A, a signal readout section 20, and a controlling section 40A. In the photodetecting section 10A, M×N pixel units P1,1 to PM,N each including a photodiode and a readout switch are arrayed in M rows and N columns. Charges generated in each pixel unit Pm,n are input to an integrating circuit Sn through a readout wiring LO,n, and a voltage value output from the integrating circuit Sn in response to the charge amount is output through a holding circuits Hn. When in a first imaging mode, a voltage value according to an amount of charges generated in the photodiode PD of each of the M×N pixel units P1,1 to PM,N in the photodetecting section 10A is output from the signal readout section 20. When in a second imaging mode, a voltage value according to an amount of charges generated in the photodiode PD of each pixel unit Pm,n included in consecutive M1 rows in the photodetecting section 10A is output from the signal readout section 20.

Abstract: A solid-state imaging device of one embodiment includes a light receiving section including of a plurality of pixels 11 having respective photodiodes, the pixels being two-dimensionally arrayed in M rows and N columns; N readout lines disposed for the respective columns and connected with the photodiodes PD included in the pixels of a respective columns via readout switches; a signal output section for outputting a voltage value according to an amount of charge input through each of the readout lines; and a vertical shift register for controlling an opening and closing operation of the readout switch for each of the rows. A contour between one side along a row direction of the light receiving section and a pair of sides along a column direction has a stepped shape. A dummy photodiode region is formed along the stepped contour of the light receiving section.

Abstract: A solid-state image pickup device 1 includes a semiconductor substrate 3A having a pixel array 10A with pixels arrayed in M rows and NA columns, a semiconductor substrate 3B having a pixel array 10B with pixels arrayed in M rows and NB columns, and a first column of which is arranged along an NA-th column of the pixel array 10A, and a signal output section 20. The signal output section 20 outputs digital values corresponding to the respective columns from the first column to the n-th column (2?n<NA) of the pixel array 10A, sequentially from the n-th column to the first column, and in parallel with this output, outputs digital values corresponding to the respective columns from the (n+1)-th column of the pixel array 10A to the NB-th column of the pixel array 10B, sequentially in a reverse order to that of the first column to the n-th column of the pixel array 10A.

Abstract: The present invention relates to a solid-state imaging device, etc., which makes it possible to obtain an image with higher resolution by properly correcting pixel data even when any one of row selecting wirings is disconnected. A solid-state imaging device (1) comprises a photodetecting section (10), a signal reading-out section (20), a controlling section (30), and a correction processing section (40). In the photodetecting section (10), M×N pixel portions P1,1 to PM,N are two-dimensionally arrayed in a matrix of M rows and N columns, and each of the pixel portions P1,1 to PM,N includes a photodiode and a reading-out switch. Charges generated in each pixel portion Pm,n are inputted into an integrating circuit Sn through a reading-out wiring LO,n, and a voltage value corresponding to the amount of charges is outputted from the integrating circuit Sn. The voltage value from the integrating circuit Sn is outputted to an output wiring Lout through a holding circuit Hn.

Abstract: A solid state imaging device 1 includes a photodetecting section 10, a signal readout section 20, a controlling section 30, and a correction processing section 40. In the photodetecting section 10, M×N pixel portions each including a photodiode which generates charges as much as an incident light intensity and a readout switch connected to the photodiode are two-dimensionally arrayed in M rows and N columns. Charges generated in each pixel portion Pm,n are input into an integration circuit Sn, through a readout wiring LO,n, and a voltage value output corresponding to the charge amount from the integration circuit Sn is output to an output wiring Lout through a holding circuit Hn. In the correction processing section 40, correction processing is performed for frame data repeatedly output from the signal readout section 20, and frame data after being subjected to the correction processing is output.

Abstract: A solid state imaging device 1 includes a photodetecting section 10, a signal readout section 20, a controlling section 30, and a correction processing section 40. In the photodetecting section 10, M×N pixel portions each including a photodiode which generates charges as much as an incident light intensity and a readout switch connected to the photodiode are two-dimensionally arrayed in M rows and N columns. Charges generated in each pixel portion Pm,n are input into an integration circuit Sn through a readout wiring LO,n, and a voltage value output corresponding to the charge amount from the integration circuit Sn is output to an output wiring Lout through a holding circuit Hn. In the correction processing section 40, correction processing is performed for frame data repeatedly output from the signal readout section 20, and frame data after being subjected to the correction processing is output.

Abstract: A solid state imaging device 1 includes a photodetecting section including M×N pixel portions P1,1 to PM,N two-dimensionally arrayed in M rows and N columns, a signal readout section including integrating circuits S1 to SN and holding circuits H1 to HN, and an initialization section including initialization switches SWI,1 to SWI,N. In response to a discharging control signal Reset, discharge switches SW2 in the integrating circuits Sn are temporarily closed and then opened, and thereafter, in response to an m-th row selecting control signal Vsel(m), the readout switches SW1 of the pixel portions Pm,n of the m-th row are closed for a first period. In this first period, in response to a hold control signal Hold, the input switches SW31 of the holding circuits Hn are switched from a closed state to an open state, and thereafter, in response to an initializing control signal Init, the initialization switches SWI,n are closed for a second period.

Abstract: A solid-state imaging device according to one embodiment includes a plurality of signal output units. Each of the plurality of signal output units includes a first input terminal electrode group that includes a plurality of terminal electrodes for inputting a reset signal, a hold signal, a horizontal start signal, and a horizontal clock signal and a first output terminal electrode that provides output signals. The solid-state imaging device further includes a second input terminal electrode group that includes a plurality of terminal electrodes for receiving the reset signal, the hold signal, the horizontal start signal, and the horizontal clock signal, a plurality of switches that switch an electrode group which is connected with integrating circuits, holding circuits, and a horizontal shift register between the first input terminal electrode group and the second input terminal electrode group, and a second output terminal electrode.

Abstract: A solid-state imaging device according to an embodiment includes a plurality of signal output units. Each of the plurality of signal output units includes an input terminal electrode group including terminal electrodes for inputting a reset signal, a hold signal, a horizontal start signal, and a horizontal clock signal and an output terminal electrode for providing an output signal. The solid-state imaging device further includes common lines that are provided across the plurality of signal output units. A terminal electrode for the reset signal and a terminal electrode for the hold signal are connected to the corresponding common lines through the corresponding switches.