Patents by Inventor Ryun Kim

Ryun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10706911
    Abstract: A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hun Seo, Kyung-Ryun Kim
  • Patent number: 10692582
    Abstract: A semiconductor memory device a memory cell array and a repair control circuit. The memory cell array including a normal cell region and a redundancy cell region, the normal cell region including a plurality of normal region groups, and redundancy cell region configured to replace failed memory cells of the normal cell region. The repair control circuit configured to, determine a target normal region group from among the plurality of normal region groups based on an input address, extract target fail addresses from among a plurality of fail addresses based on the target normal region group, and control a repair operation based on the target fail addresses and the input address.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Ryun Kim
  • Patent number: 10635535
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Kyung-Ryun Kim, Young-Hun Seo
  • Patent number: 10510429
    Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-yong Choi, Kyung-ryun Kim, Woong-dai Kang, Hyun-chul Yoon
  • Patent number: 10497460
    Abstract: A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun Kim, Hyun-Chul Yoon
  • Patent number: 10480032
    Abstract: The present disclosure relates to a novel use of EI24, and provides a novel use of EI24 involved in the improvement of EGFR-TKI drug resistance by inhibiting IGF-1R signaling. According to the present disclosure, the presence or absence of resistance to anti-cancer drugs may be determined by detecting an expression level of EI24. In addition, resistance to anti-cancer drugs may be inhibited, delayed, or improved using EI24 or an activating agent thereof. Moreover, by regulating a pathway of EI24-mediated resistance to anti-cancer drugs, the efficacy of existing anti-cancer drugs may be enhanced, and resistance to anti-cancer drugs may be inhibited, delayed, or improved.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: November 19, 2019
    Assignee: University-Industry Foundation, Yonsei University
    Inventors: Han Woong Lee, Jung-Min Choi, Byoung Chul Cho, Yu-Ra Choi, Ji-Young Jang, Hye Ryun Kim
  • Publication number: 20190304565
    Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
    Type: Application
    Filed: February 22, 2019
    Publication date: October 3, 2019
    Inventors: Kyung-Ryun KIM, Yoon-Na OH, Hyung-Jin KIM, Hui-Kap YANG, Jang-Woo RYU
  • Publication number: 20190243708
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.
    Type: Application
    Filed: November 9, 2018
    Publication date: August 8, 2019
    Inventors: SANG-UHN CHA, KYUNG-RYUN KIM, YOUNG-HUN SEO
  • Publication number: 20190164621
    Abstract: A semiconductor memory device a memory cell array and a repair control circuit. The memory cell array including a normal cell region and a redundancy cell region, the normal cell region including a plurality of normal region groups, and redundancy cell region configured to replace failed memory cells of the normal cell region. The repair control circuit configured to, determine a target normal region group from among the plurality of normal region groups based on an input address, extract target fail addresses from among a plurality of fail addresses based on the target normal region group, and control a repair operation based on the target fail addresses and the input address.
    Type: Application
    Filed: September 13, 2018
    Publication date: May 30, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Ryun KIM
  • Publication number: 20190130987
    Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.
    Type: Application
    Filed: June 13, 2018
    Publication date: May 2, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-yong CHOI, Kyung-ryun KIM, Woong-dai KANG, Hyun-chul YOON
  • Publication number: 20190096508
    Abstract: A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.
    Type: Application
    Filed: June 29, 2018
    Publication date: March 28, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun KIM, Hyun-Chul YOON
  • Patent number: 10227637
    Abstract: Provided are a PNA probe for detecting nucleotide polymorphism of a target gene, a melting curve analysis method for detecting the nucleotide polymorphism of the target gene using the same, a nucleotide polymorphism analysis method of a target gene including the melting curve analysis method, and a kit for detecting the nucleotide polymorphism of the target gene containing the PNA probe. It is characterized that the PNA probe according to the present invention contains negative charge molecules. The modified PNA probe according to the present invention contains the negative charge molecules to have a high recognition ability with respect to a target DNA and a high coupling ability to the target DNA and to be rapidly dissociated by heat, such that the nucleotide polymorphism analysis may be relatively easily performed even in a heterozygous sample showing two melting curve graphs, and two or more adjacent single nucleotide polymorphisms may be simultaneously analyzed.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 12, 2019
    Assignee: PANAGENE INC.
    Inventors: Goon Ho Joe, Sung-Kee Kim, Heekyung Park, Chwang Siek Park, Se Ryun Kim, Yongtae Kim, Su Nam Kim
  • Patent number: 10192006
    Abstract: Provided is a method of the simulation construction for measurement of the control rod insertion time including a three-dimensional modeling operation of an inside wall of the nuclear reactor, a control rod, etc; a flow field configuration operation wherein the flow field is differentially configured by a variable grid system comprising variable cells which change the configuration and by an aligned grid system comprising fixed cells which maintains the configuration; a calculation operation of simulation estimated value for the insertion time by analyzing the thermal-hydraulic phenomenon using the three-dimensional CFD; and a cell change operation, wherein an error between the estimated value and the actual value is verified whether the error lies within the reference range, and, when the error exceeds the reference range, the size of the variable cell and/or of the size of the fixed cell is changed.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: January 29, 2019
    Assignee: KEPCO ENGINEERING & CONSTRUCTION COMPANY, INC.
    Inventors: Kyoung Ryun Kim, Cheol Shin Lee
  • Patent number: 10018861
    Abstract: A display device is disclosed which includes: a liquid crystal panel; an optical member configured to apply light to the liquid crystal panel; and a wrapping film configured to wrap an upper surface, at least one side surface and at least a part of a lower surface of the optical member.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: July 10, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jin Ryun Kim, Won Taek Moon, Sang Hyun Lee, Su Jin Chang, Seoung Mo Kang
  • Patent number: 9965005
    Abstract: A memory diagnosis system includes a memory device and a server. The memory device includes a memory module configured to adjust operational parameters in response to a parameter control signal, a memory controller configured to generate the parameter control signal in response to a feedback signal, and a memory state monitor configured to monitor the memory module to generate an information signal that includes information on a state of the memory module. The server is configured to generate the feedback signal in response to the information signal.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: May 8, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun Kim, Ki-Tae Park
  • Patent number: 9921749
    Abstract: A method of operating a memory system, including a memory device, includes managing program order information of the memory device based on a program order stamp (POS) indicating a relative temporal relationship between program operations of a plurality of memory groups that are included in the memory device. The method includes generating a first mapping table that stores a read voltage offset and an upper POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially decreased or reduced, and generating a second mapping table that stores the read voltage offset and a lower POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially increased. A read voltage for performing a read operation on the memory device is variably determined based on the first and second mapping tables and the program order information.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Ryun Kim, Joon-Suc Jang
  • Patent number: 9858014
    Abstract: A method of operating a memory system includes managing program order information of the memory device based on program order stamps (POSs) indicating relative temporal relationships between program operations performed in relation to a plurality of memory groups included in the memory device, and controlling operations directed to the plurality of memory groups in response to the program order information.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Ryun Kim
  • Patent number: 9812213
    Abstract: A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun Kim, Sang-Yong Yoon
  • Publication number: 20170309181
    Abstract: An apparatus for recognizing a following vehicle includes a rear radar for detecting an object located in the rear of a subject vehicle, a guardrail area detector for detecting a guardrail area of a road using a road image of front of the subject vehicle and an image of a stationary object among objects detected by the rear radar, and a following vehicle recognizing unit for recognizing, as a following vehicle, a vehicle located on a road in the same traveling direction as that of the subject vehicle among objects detected by the rear radar, wherein the following vehicle is not included in the guardrail area detected by the guardrail area detector.
    Type: Application
    Filed: April 26, 2017
    Publication date: October 26, 2017
    Inventors: Hoon LEE, Seongkeun PARK, Hyun Ju KIM, Min Kyun YOO, Ju Yun RO, Young Won KIM, Bong Sob SONG, Gi Hyun HAN, Tae Ryun KIM, Jin Hyeon PARK
  • Publication number: 20170268067
    Abstract: The present disclosure relates to a novel use of EI24, and provides a novel use of EI24 involved in the improvement of EGFR-TKI drug resistance by inhibiting IGF-1R signaling. According to the present disclosure, the presence or absence of resistance to anti-cancer drugs may be determined by detecting an expression level of EI24. In addition, resistance to anti-cancer drugs may be inhibited, delayed, or improved using EI24 or an activating agent thereof. Moreover, by regulating a pathway of EI24-mediated resistance to anti-cancer drugs, the efficacy of existing anti-cancer drugs may be enhanced, and resistance to anti-cancer drugs may be inhibited, delayed, or improved.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 21, 2017
    Inventors: Han Woong LEE, Jung-Min CHOI, Byoung Chul CHO, Yu-Ra CHOI, Ji-Young JANG, Hye Ryun KIM