Abstract: It is an object to provide technology enabling suppression of scattering of metal powder during ultrasonic bonding to suppress discharge and abnormal operation of a semiconductor device. A semiconductor device includes: an insulating substrate including an insulating layer and a metal pattern disposed on the insulating layer; and an electrode bonded on the metal pattern. The electrode includes, in a portion inward of a peripheral portion of a bonded surface being a surface of the electrode bonded on the metal pattern, a receiving portion recessed upward and capable of receiving metal powder generated during bonding of the electrode and the metal pattern, and the peripheral portion of the bonded surface of the electrode is bonded on the metal pattern.

Abstract: An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part. The sealing member covers the plurality of semiconductor chips, and parts being connected to the plurality of semiconductor chips, of the plurality of electrodes. The joint part is disposed outside the sealing member to electrically connect parts which are not covered by the sealing member, of the plurality of electrodes.

Abstract: Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.

Abstract: First and second circuit patterns (5,6) are provided on an insulating substrate (1). First and second semiconductor chips (7,8) are provided on the first circuit pattern (5). A relay circuit pattern (10) is provided between the first semiconductor chip (7) and the second semiconductor chip (8) on the insulating substrate (1). A wire (11) is continuously connected to the first semiconductor chip (7), the relay circuit pattern (10), the second semiconductor chip (8) and the second circuit pattern (6) which are sequentially arranged in one direction.

Abstract: A wiring board (2) is provided on a heat radiation plate (1). A semiconductor chip (8) is provided on the wiring board (2). A case housing (10) is provided on the heat radiation plate (1) and surrounds the wiring board (2) and the semiconductor chip (8). Adhesive agent (11) bonds a lower surface of the case housing (10) and an upper surface peripheral portion of the heat radiation plate (1). A sealing material (13) is filled in the case housing (10) and covers the wiring board (2) and the semiconductor chip (8). A step portion (16,17) is provided to at least one of the lower surface of the case housing (10) and the upper surface peripheral portion of the heat radiation plate (1). A side surface of the heat radiation plate (1) and an outer side surface of the case housing (10) are flush with each other.

Abstract: Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.

Abstract: First and second circuit patterns (5,6) are provided on an insulating substrate (1). First and second semiconductor chips (7,8) are provided on the first circuit pattern (5). A relay circuit pattern (10) is provided between the first semiconductor chip (7) and the second semiconductor chip (8) on the insulating substrate (1). A wire (11) is continuously connected to the first semiconductor chip (7), the relay circuit pattern (10), the second semiconductor chip (8) and the second circuit pattern (6) which are sequentially arranged in one direction.

Abstract: An object of the present invention to provide a technique which can put flexibility into positions, positional relationships, and sizes of constituent elements. A power semiconductor device includes: a substrate on which a semiconductor chip is disposed; an electrode which has one end fixed to the substrate and stands upright on the substrate; and an insulating case which houses the electrode and has a part opposed to the other end of the electrode. The power semiconductor device includes a conductive nut which is inserted into the case in the part of the case and a conductive component which electrically connects the other end of the electrode and the nut.

Abstract: It is an object of the present invention to provide a semiconductor device which allows an increase in the number of semiconductor elements mounted in parallel and prevents a shape of an insulating substrate onto which the semiconductor elements are mounted, from being laterally long, and provide a semiconductor module including such semiconductor device. A semiconductor device according to the present invention includes an insulating substrate, a metal pattern which is a continuous piece and is bonded to one main surface of the insulating substrate, and a plurality of switching elements which are bonded to a surface opposite to the insulating substrate on the metal pattern, and the plurality of switching elements are arranged in a matrix of two or more rows and two or more columns on the metal pattern.

Abstract: A wiring board (2) is provided on a heat radiation plate (1). A semiconductor chip (8) is provided on the wiring board (2). A case housing (10) is provided on the heat radiation plate (1) and surrounds the wiring board (2) and the semiconductor chip (8). Adhesive agent (11) bonds a lower surface of the case housing (10) and an upper surface peripheral portion of the heat radiation plate (1). A sealing material (13) is filled in the case housing (10) and covers the wiring board (2) and the semiconductor chip (8). A step portion (16,17) is provided to at least one of the lower surface of the case housing (10) and the upper surface peripheral portion of the heat radiation plate (1). A side surface of the heat radiation plate (1) and an outer side surface of the case housing (10) are flush with each other.

Abstract: A base plate, and a plurality of unit structures formed on the base plate are provided. Each of the unit structures including an insulating substrate fixed on the base plate, a metal pattern formed on the insulating substrate, a semiconductor element electrically connected to the metal pattern, and a main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate.

Abstract: It is an object of the present invention to provide a semiconductor module that reduces an excessive stress on a sealed object due to the expansion and contraction of a sealing gel to thus improve the reliability. A semiconductor module according to the present invention includes: a semiconductor element bonded to a metal pattern on an insulating substrate contained in a case; a sealing gel sealing the insulating substrate and the semiconductor element within the case; and a sealing-gel-expansion suppressing plate disposed in the upper portion of the sealing gel to be at least partially in contact with the sealing gel. The sealing-gel-expansion suppressing plate includes a surface facing the sealing gel and inclined to the upper surface of the sealing gel.

Abstract: An object of the present invention to provide a technique which can put flexibility into positions, positional relationships, and sizes of constituent elements. A power semiconductor device includes: a substrate on which a semiconductor chip is disposed; an electrode which has one end fixed to the substrate and stands upright on the substrate; and an insulating case which houses the electrode and has a part opposed to the other end of the electrode. The power semiconductor device includes a conductive nut which is inserted into the case in the part of the case and a conductive component which electrically connects the other end of the electrode and the nut.

Abstract: It is an object of the present invention to provide a semiconductor device which allows an increase in the number of semiconductor elements mounted in parallel and prevents a shape of an insulating substrate onto which the semiconductor elements are mounted, from being laterally long, and provide a semiconductor module including such semiconductor device. A semiconductor device according to the present invention includes an insulating substrate, a metal pattern which is a continuous piece and is bonded to one main surface of the insulating substrate, and a plurality of switching elements which are bonded to a surface opposite to the insulating substrate on the metal pattern, and the plurality of switching elements are arranged in a matrix of two or more rows and two or more columns on the metal pattern.

Abstract: An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part. The sealing member covers the plurality of semiconductor chips, and parts being connected to the plurality of semiconductor chips, of the plurality of electrodes. The joint part is disposed outside the sealing member to electrically connect parts which are not covered by the sealing member, of the plurality of electrodes.

Abstract: It is an object of the present invention to provide a semiconductor module that reduces an excessive stress on a sealed object due to the expansion and contraction of a sealing gel to thus improve the reliability. A semiconductor module according to the present invention includes: a semiconductor element bonded to a metal pattern on an insulating substrate contained in a case; a sealing gel sealing the insulating substrate and the semiconductor element within the case; and a sealing-gel-expansion suppressing plate disposed in the upper portion of the sealing gel to be at least partially in contact with the sealing gel. The sealing-gel-expansion suppressing plate includes a surface facing the sealing gel and inclined to the upper surface of the sealing gel.

Abstract: An electrode (3) is joined to a wiring substrate (2). A nut box (7) is inserted in the bent portion (5) of the electrode (3) so that the nut (6) is positioned in alignment with the opening (4) of the electrode (3). A case (8) covers the wiring substrate (2). The nut box (7) and the case (8) are members separate from each other. The nut box (7) is fixed in the electrode (3) so as not to come off from the bent portion 5).