Abstract: It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina.

Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.

Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

Abstract: A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.

Abstract: In aspects of the present invention, a lamina is formed having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous.

Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

Abstract: Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.

Abstract: Low-relief texture can be created by applying and firing frit paste on a silicon surface. Where frit contacts the surface at high temperature, it etches silicon, dissolving silicon in the softened glass frit. The result is a series of small, randomly located pits, which produce a near-Lambertian surface, suitable for use in a photovoltaic cell. This texturing method consumes little silicon, and is advantageously used in a photovoltaic cell in which a thin silicon lamina comprises the base region of the cell. When the lamina is formed by implanting ions in a donor wafer to form a cleave plane and cleaving the lamina from the donor wafer at the cleave plane, the ion implantation step will serve to translate texture formed at a first surface to the cleave plane, and thus to the second, opposing surface following cleaving. Low-relief texture formed by other methods can be translated from the first surface to the second surface in this way as well.

Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, and forming a reversible resistance-switching element coupled to the steering element. The reversible resistance-switching element includes one or more of TiOx, Ta2O5, Nb2O5, Al2O3, HfO2, and V2O5, and the reversible resistance switching element is formed without being etched. Numerous other aspects are provided.

Abstract: A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a transparent conductive oxide layer serving as a quarter-wave plate, a low resistance layer, an adhesion layer to help adhesion to the receiver element, and may also include a barrier layer to prevent or impede unwanted diffusion within the stack.

Abstract: A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.

Abstract: A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.

Abstract: One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

Abstract: In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.

Abstract: A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a titanium layer in contact with the lamina, which reacts to form titanium silicide, a non-reactive barrier layer to check the silicide reaction, a low-resistance layer, and an adhesion layer to help adhesion to the receiver element.

Abstract: In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM antifuse stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM antifuse stack. Other aspects are provided.

Abstract: A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.

Abstract: A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb2O5, TiO2, HfO2, Al2O3, CoO, MgOx, CrO2, VO, BN, and AlN. Numerous other aspects are provided.

Abstract: A monolithic three dimensional memory array is provided that includes a first memory level formed above a substrate, and a second memory level monolithically formed above the first memory level. The first memory level includes a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction, a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction, the second direction different from the first direction, the second conductors above the first conductors, and a first plurality of devices. Each of the first plurality of devices is disposed between one of the first conductors and one of the second conductors, and includes a resistivity-switching binary metal oxide or nitride compound and a silicon, germanium, or silicon-germanium alloy resistor of a single conductivity type. Numerous other aspects are provided.

Abstract: A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.