Abstract: Low-relief texture can be created by applying and firing frit paste on a silicon surface. Where frit contacts the surface at high temperature, it etches silicon, dissolving silicon in the softened glass frit. The result is a series of small, randomly located pits, which produce a near-Lambertian surface, suitable for use in a photovoltaic cell. This texturing method consumes little silicon, and is advantageously used in a photovoltaic cell in which a thin silicon lamina comprises the base region of the cell. When the lamina is formed by implanting ions in a donor wafer to form a cleave plane and cleaving the lamina from the donor wafer at the cleave plane, the ion implantation step will serve to translate texture formed at a first surface to the cleave plane, and thus to the second, opposing surface following cleaving. Low-relief texture formed by other methods can be translated from the first surface to the second surface in this way as well.

Abstract: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.

Abstract: The surface of a conductive layer such as a conductive nitride, a conductive silicide, a metal, or metal alloy or compound, is exposed to a dopant gas which provides an n-type or p-type dopant. The dopant gas may be included in a plasma. Semiconductor material, such as silicon, germanium, or their alloys, is deposited directly on the surface which has been exposed to the dopant gas. During and subsequent to deposition, dopant atoms diffuse into the deposited semiconductor, forming a thin heavily doped region and making a good ohmic contact between the semiconductor material and the underlying conductive layer.

Abstract: Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.

Abstract: A microelectronic structure including a layerstack is provided, the layerstack including: (a) a first layer including semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, the first layer being between about 50 and 200 angstroms thick, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration; (b) a second layer including semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer includes heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant conce

Abstract: A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device.

Abstract: In aspects of the present invention, a lamina is formed having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous.

Abstract: In aspects of the present invention, a method is disclosed to form a lamina having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous.

Abstract: It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina.

Abstract: A photovoltaic device is disclosed herein that, in various aspects, includes a conductive layer, and a substantially crystalline lamina with a first surface oriented toward the conductive layer and a second surface oriented away from the conductive layer. The lamina thickness is within the range between about 0.2 microns and about 50 microns. An aperture passes through the lamina from the first surface to the second surface. A connector in electrical communication with the conductive layer is disposed through the aperture. Methods of manufacture of the photovoltaic devise are also disclosed.

Abstract: A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.

Abstract: A method is described for monolithically forming a first memory level above a substrate, the method including: (a) forming a plurality of first substantially parallel, substantially coplanar conductors above the substrate, the first conductors extending in a first direction; (b) forming a plurality of vertically oriented contiguous p-i-n diodes above the first conductors, the contiguous p-in diode comprising semiconductor material crystallized in contact with a silicide, silicide-germanide, or germanide layer; (c) forming a plurality of second substantially parallel, substantially coplanar conductors, the second conductors above the contiguous p-i-n diodes, the second conductors extending in a second direction different from the first direction, each contiguous p-i-n diode vertically disposed between one of the first conductors and one of the second conductors; (d) and forming a plurality of dielectric rupture antifuses, each dielectric rupture antifuse disposed between one of the contiguous p-i-n diodes and

Abstract: A nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits is described. To form this cell, a conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.

Abstract: A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

Abstract: A method is described for forming a nonvolatile one-time-programmable memory cell having reduced programming voltage. A contiguous p-i-n diode is paired with a dielectric rupture antifuse formed of a high-dielectric-constant material, having a dielectric constant greater than about 8. In preferred embodiments, the high-dielectric-constant material is formed by atomic layer deposition. The diode is preferably formed of deposited low-defect semiconductor material, crystallized in contact with a silicide. A monolithic three dimensional memory array of such cells can be formed in stacked memory levels above the wafer substrate.

Abstract: A method to form a rewriteable nonvolatile memory cell is disclosed, the cell comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.

Abstract: A photovoltaic cell can be formed from a thin semiconductor lamina cleaved from a substantially crystalline wafer. Shunts may inadvertently be formed through such a lamina, compromising device performance. By physically severing the lamina into a plurality of segments, the segments of the lamina preferably electrically connected in series, loss of efficiency due to shunt formation may be substantially reduced. In some embodiments, adjacent laminae are connected in series into strings, and the strings are connected in parallel to compensate for the reduction in current caused by severing the lamina into segments.

Abstract: A photovoltaic cell can be formed from a thin semiconductor lamina cleaved from a substantially crystalline wafer. Shunts may inadvertently be formed through such a lamina, compromising device performance. By physically severing the lamina into a plurality of segments, the segments of the lamina preferably electrically connected in series, loss of efficiency due to shunt formation may be substantially reduced. In some embodiments, adjacent laminae are connected in series into strings, and the strings are connected in parallel to compensate for the reduction in current caused by severing the lamina into segments.

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.