Abstract: A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in an ion metal plasma chamber with no self-bias accelerating ions normal to the deposition surface, or in a standard PVD chamber with pressure increased.

Abstract: A three dimensional monolithic memory comprising a memory cell allowing for increased density is disclosed. In the memory cell of the present invention, a bottom conductor preferably comprising tungsten is formed. Above the bottom conductor a semiconductor element preferably comprises two diode portions and an antifuse. Above the semiconductor element are additional conductors and semiconductor elements in multiple stones of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Abstract: The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.

Abstract: The invention provides for a vertically oriented junction diode having a contact-antifuse unit in contact with one of its electrodes. The contact-antifuse unit is formed either above or below the junction diode, and comprises a silicide with a dielectric antifuse layer formed on and in contact with it. In preferred embodiments, the silicide is cobalt silicide, and the antifuse preferably silicon oxide, silicon nitride, or silicon oxynitride grown on the colbalt silicide. The junction diode and contact-antifuse unit can be used as a memory cell, which is advantageously used in a monolithic three dimensional memory array.

Abstract: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.

Abstract: A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in an ion metal plasma chamber with no self-bias accelerating ions normal to the deposition surface, or in a standard PVD chamber with pressure increased.

Abstract: A method to create a low resistivity P+in-situ doped polysilicon film at low temperature from SiH4 and BCl3 with no anneal required. At conventional dopant concentrations using these source gases, as deposition temperature decreases below about 550 degrees C., deposition rate decreases and sheet resistance increases, making production of a high-quality film impossible. By flowing very high amounts of BCl3, however, such that the concentration of boron atoms in the resultant film is about 7×1020 or higher, the deposition rate and sheet resistance are improved, and a high-quality film is produced.

Abstract: A method to create a low resistivity P+ in-situ doped polysilicon film at low temperature from SiH4 and BCl3 with no anneal required. At conventional dopant concentrations using these source gases, as deposition temperature decreases below about 550 degrees C., deposition rate decreases and sheet resistance increases, making production of a high-quality film impossible. By flowing very high amounts of BCl3, however, such that the concentration of boron atoms in the resultant film is about 7×1020 or higher, the deposition rate and sheet resistance are improved, and a high-quality film is produced.

Abstract: A semiconductor device, such as an inverted staggered thin film transistor, includes a gate electrode, a gate insulating layer located above the gate electrode, an active layer located above the gate insulating layer and an insulating fill layer located above the active layer. A first opening and a second opening are located in the insulating fill layer, a first source or drain electrode is located in the first opening and a second source or drain electrode is located in the second opening. At least one of the first and the second source or drain electrodes comprise a polysilicon layer and a metal silicide layer.

Abstract: A method to create a low resistivity P+ in-situ doped polysilicon film at low temperature from SiH4 and BCl3 with no anneal required. At conventional dopant concentrations using these source gases, as deposition temperature decreases below about 550 degrees C., deposition rate decreases and sheet resistance increases, making production of a high-quality film impossible. By flowing very high amounts of BCl3, however, such that the concentration of boron atoms in the resultant film is about 7×1020 or higher, the deposition rate and sheet resistance are improved, and a high-quality film is produced.

Abstract: A thin film transistor with a channel less than 100 angstroms thick, preferably less than 80 angstroms thick, preferably less than 60 angstroms thick. The very thin channel reduces variability of threshold voltage from one TFT to the next. This is particularly advantageous for TFT memory arrays. It is possible that an extremely thin channel restricts the size of grains, forcing many small grains to be formed.

Abstract: A thin dielectric layer grown on a silicide layer can be used in many semiconductor devices. Such a grown dielectric, which may be, for example, a silicon oxide, silicon nitride, or silicon oxynitride dielectric layer, can advantageously be used as a dielectric antifuse. Such an antifuse paired with a diode or diode portions can operate as a memory cell, which is unprogrammed before rupture and programmed after rupture. Memory cell types using a dielectric grown on a silicide include Schottky diode portions separated by an antifuse, a Schottky diode separated from an adjacent conductor by an antifuse, and a junction diode separated from an adjacent conductor by an antifuse.

Abstract: A semiconductor device, such as an inverted staggered thin film transistor, includes a gate electrode, a gate insulating layer located above the gate electrode, an active layer located above the gate insulating layer and an insulating fill layer located above the active layer. A first opening and a second opening are located in the insulating fill layer, a first source or drain electrode is located in the first opening and a second source or drain electrode is located in the second opening. At least one of the first and the second source or drain electrodes comprise a polysilicon layer and a metal silicide layer.

Abstract: Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.

Abstract: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.