Patents by Inventor Sachiko Aoi

Sachiko Aoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220005928
    Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.
    Type: Application
    Filed: September 16, 2021
    Publication date: January 6, 2022
    Inventors: Yuichi TAKEUCHI, Ryota SUZUKI, Tatsuji NAGAOKA, Sachiko AOI
  • Patent number: 11177353
    Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 16, 2021
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Ryota Suzuki, Tatsuji Nagaoka, Sachiko Aoi
  • Patent number: 11063145
    Abstract: A silicon carbide semiconductor device includes: a substrate; a first impurity region on the substrate; a base region on the first impurity region; a second impurity region in the base region; a trench gate structure including a gate insulation film and a gate electrode in a trench; a first electrode connected to the second impurity region and the base region; a second electrode on a rear surface of the substrate; a first current dispersion layer between the first impurity region and the base region; a plurality of first deep layers in the second current dispersion layer; a second current dispersion layer between the first current dispersion layer and the base region; and a second deep layer between the first current dispersion layer and the base region apart from the trench.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: July 13, 2021
    Assignee: DENSO CORPORATION
    Inventors: Shuhei Mitani, Aiko Kaji, Yasuhiro Ebihara, Tatsuji Nagaoka, Sachiko Aoi
  • Patent number: 11049966
    Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: June 29, 2021
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akira Amano, Takayuki Satomura, Yuichi Takeuchi, Katsumi Suzuki, Sachiko Aoi
  • Patent number: 10923395
    Abstract: In a semiconductor device, a semiconductor element is formed in a semiconductor, an interlayer insulating film having a contact hole and containing at least one of phosphorus and boron is disposed above the semiconductor, a metal electrode is disposed above the interlayer insulating film and is connected to the semiconductor element through the contact hole, and the interlayer insulating film is filled with hydrogen.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: February 16, 2021
    Assignee: DENSO CORPORATION
    Inventors: Yasushi Urakami, Takehiro Kato, Sachiko Aoi
  • Publication number: 20200381313
    Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Inventors: Akira AMANO, Takayuki SATOMURA, Yuichi TAKEUCHI, Katsumi SUZUKI, Sachiko AOI
  • Patent number: 10790201
    Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: September 29, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akira Amano, Takayuki Satomura, Yuichi Takeuchi, Katsumi Suzuki, Sachiko Aoi
  • Patent number: 10770580
    Abstract: In an end portion of a trench, an opening where the end portion of the trench is exposed is formed in a lead-out electrode, a side surface of the trench gate electrode on a top surface side of a semiconductor substrate is spaced from a trench side surface, and a range adjacent to a boundary line positioned between a top surface of the semiconductor substrate and the trench side surface is covered with a laminated insulating film configured such that an interlayer insulating film is laminated on a gate insulating film. This makes it possible to prevent dielectric breakdown of an insulating film.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 8, 2020
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Toru Onishi, Sachiko Aoi, Yasushi Urakami
  • Patent number: 10748780
    Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and on which a base layer is formed is prepared, a trench is provided in the base layer, a silicon carbide layer is epitaxially formed on a surface of the base layer while filling the trench with the silicon carbide layer, the sacrificial layer is planarized by reflow after forming the sacrificial layer, and the silicon carbide layer is etched back together with the planarized sacrificial layer by dry etching under an etching condition in which an etching selectivity of the silicon carbide layer to the sacrificial layer is 1.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 18, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shigeyuki Takagi, Masaki Shimomura, Yuichi Takeuchi, Katsumi Suzuki, Sachiko Aoi
  • Patent number: 10714611
    Abstract: A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: July 14, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Atsuya Akiba, Sachiko Aoi, Katsumi Suzuki
  • Publication number: 20200168732
    Abstract: A silicon carbide semiconductor device includes: a substrate; a first impurity region on the substrate; a base region on the first impurity region; a second impurity region in the base region; a trench gate structure including a gate insulation film and a gate electrode in a trench; a first electrode connected to the second impurity region and the base region; a second electrode on a rear surface of the substrate; a first current dispersion layer between the first impurity region and the base region; a plurality of first deep layers in the second current dispersion layer; a second current dispersion layer between the first current dispersion layer and the base region; and a second deep layer between the first current dispersion layer and the base region apart from the trench.
    Type: Application
    Filed: January 30, 2020
    Publication date: May 28, 2020
    Inventors: Shuhei MITANI, Aiko KAJI, Yasuhiro EBIHARA, Tatsuji NAGAOKA, Sachiko AOI
  • Patent number: 10643851
    Abstract: A compound semiconductor device includes a semiconductor substrate having a ground layer of a first conductivity type made of a compound semiconductor, a first conductivity type region formed at a corner portion of a bottom of a deep trench formed to the ground layer, and a deep layer of a second conductivity type formed in the deep trench so as to cover the first conductivity type region. A cross section of the first conductivity type region is a triangular shape or a rounded triangular shape in which a portion of the first conductivity type region being in contact with the deep layer is recessed to have a curved surface.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 5, 2020
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Atsuya Akiba, Katsumi Suzuki, Sachiko Aoi
  • Publication number: 20200052112
    Abstract: In an end portion of a trench, an opening where the end portion of the trench is exposed is formed in a lead-out electrode, a side surface of the trench gate electrode on a top surface side of a semiconductor substrate is spaced from a trench side surface, and a range adjacent to a boundary line positioned between a top surface of the semiconductor substrate and the trench side surface is covered with a laminated insulating film configured such that an interlayer insulating film is laminated on a gate insulating film. This makes it possible to prevent dielectric breakdown of an insulating film.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 13, 2020
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Toru ONISHI, Sachiko AOI, Yasushi URAKAMI
  • Publication number: 20190341308
    Abstract: In a semiconductor device, a semiconductor element is formed in a semiconductor, an interlayer insulating film having a contact hole and containing at least one of phosphorus and boron is disposed above the semiconductor, a metal electrode is disposed above the interlayer insulating film and is connected to the semiconductor element through the contact hole, and the interlayer insulating film is filled with hydrogen.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Yasushi URAKAMI, Takehiro KATO, Sachiko AOI
  • Publication number: 20190334030
    Abstract: A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Yuichi TAKEUCHI, Atsuya AKIBA, Sachiko AOI, Katsumi SUZUKI
  • Publication number: 20190288074
    Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Inventors: Yuichi TAKEUCHI, Ryota SUZUKI, Tatsuji NAGAOKA, Sachiko AOI
  • Patent number: 10374081
    Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of this element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench; and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region, and in contact with the gate insulation layer on a lower side of the body region. The bottom region includes a low concentration region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench; and a high concentration region in contact with the gate insulation layer in a second range of the bottom surface adjacent to the first range.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: August 6, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Sachiko Aoi, Yasushi Urakami
  • Patent number: 10367091
    Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of the element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench, and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region. The bottom region includes a first bottom region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench and extending from the bottom surface to a first position; and a second bottom region in contact with the gate insulation layer in a second range adjacent to the first range and extending from the bottom surface to a second position lower than the first position.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: July 30, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Sachiko Aoi, Yasushi Urakami
  • Publication number: 20190214264
    Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and on which a base layer is formed is prepared, a trench is provided in the base layer, a silicon carbide layer is epitaxially formed on a surface of the base layer while filling the trench with the silicon carbide layer, the sacrificial layer is planarized by reflow after forming the sacrificial layer, and the silicon carbide layer is etched back together with the planarized sacrificial layer by dry etching under an etching condition in which an etching selectivity of the silicon carbide layer to the sacrificial layer is 1.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: Shigeyuki TAKAGI, Masaki SHIMOMURA, Yuichi TAKEUCHI, Katsumi SUZUKI, Sachiko AOI
  • Patent number: 10326015
    Abstract: A switching element may include a semiconductor substrate, first and second trenches, a gate insulating layer, an interlayer insulating layer covering the semiconductor substrate, and an electrode on the interlayer insulating layer. A wide portion and a narrow portion may be arranged alternately between the first and second trenches. The interlayer insulating layer may include a contact hole in the wide portion. The electrode may be in contact with the semiconductor substrate within the contact hole. The semiconductor substrate may include an upper n-type region in contact with the gate insulating layer in the narrow portion and in contact with the electrode, a p-type body contact region in contact with the electrode, a p-type body region in contact with the gate insulating layer in the narrow portion, and a lower n-type region in contact with the gate insulating layer in the narrow portion.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 18, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masatoshi Tsujimura, Katsuhiro Kutsuki, Sachiko Aoi, Yasushi Urakami