Patents by Inventor Sachiko Kobayashi

Sachiko Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6622297
    Abstract: A pattern of exposure mask-use design data having a hierarchical structure is corrected in order to finish with fidelity a transfer pattern to be formed on a wafer, in which if the exposure apparatus has a light source shape that does not have rotation symmetry at any given angle around an optical axis, as the center, of an illumination optics or a projection optics, a cell A rotated in arrangement in input data having a hierarchical structure is replaced with a cell A′ not employing rotation and then optical proximity correction is effected.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: September 16, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taiga Uno, Kazuko Yamamoto, Sachiko Kobayashi, Satoshi Tanaka
  • Publication number: 20030126582
    Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 3, 2003
    Inventors: Sachiko Kobayashi, Toshiya Kotani, Satoshi Tanaka, Susumu Watanabe, Mitsuhiro Yano
  • Publication number: 20030074646
    Abstract: A mask pattern generation method of generating a mask pattern from a designed pattern, comprising preparing the designed pattern, preparing a correction parameter, preparing a first correction library in which a plurality of pairs of an edge coordinate group and a correction value group to correct the edge coordinate group is registered, acquiring edge coordinate groups of the designed patterns, generating a second correction library in which only the plurality of pairs of an edge coordinate group agreeing with the acquired edge coordinate group and the correction value group is registered in the first correction library and simulation using the correction parameter, and correcting the designed pattern using the second correction library.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 17, 2003
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue, Sachiko Kobayashi, Hirotaka Ichikawa
  • Publication number: 20020040468
    Abstract: A pattern of exposure mask-use design data having a hierarchical structure is corrected in order to finish with fidelity a transfer pattern to be formed on a wafer, in which if the exposure apparatus has a light source shape that does not have rotation symmetry at any given angle around an optical axis, as the center, of an illumination optics or a projection optics, a cell A rotated in arrangement in input data having a hierarchical structure is replaced with a cell A′ not employing rotation and then optical proximity correction is effected.
    Type: Application
    Filed: September 21, 2001
    Publication date: April 4, 2002
    Inventors: Taiga Uno, Kazuko Yamamoto, Sachiko Kobayashi, Satoshi Tanaka
  • Patent number: 6243855
    Abstract: A correction target segment extracted from the design pattern is divided into lengths suited for correction. If the arrangement of the divided segments is a one-dimensional pattern, a correction value is obtained by conducting a one-dimensional process simulation to an arrangement within a predetermined distance from a divided segment in perpendicular direction. If the arrangement of the divided segments is a two-dimensional pattern, a correction value is obtained by two-dimensionally extracting a pattern included in a rectangular region having a predetermined distance from one point on the divided segment in perpendicular and horizontal directions and by conducting a two-dimensional process simulation to the extracted pattern.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: June 5, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sachiko Kobayashi, Taiga Uno, Kazuko Yamamoto, Koji Hashimoto
  • Patent number: 6110647
    Abstract: A method of manufacturing a semiconductor device, comprises the steps of forming a first transfer pattern corresponding to a mask pattern on a major surface side of a semiconductor substrate through a first mask plate on which the first mask pattern having a straight portion and a bent portion is formed, and forming a second transfer pattern corresponding to a second mask pattern on a major surface side of the semiconductor substrate through a second mask plate on which the second mask pattern having a pattern arranged at a position corresponding to the straight portion is formed.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: August 29, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Hisashi Kaneko, Masahiko Hasunuma, Takamasa Usui, Masami Aoki, Kazuko Yamamoto, Sachiko Kobayashi
  • Patent number: 6060368
    Abstract: This invention is provided to eliminate the optical proximity effect which will occur because of different rates of dimensional change between before and after etching when a plurality of gate materials are etched in a single device. After a to-be-corrected region is extracted, an n.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the n.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be a p.sup.+ -type polysilicon gate layer, thereby correcting the size of the n.sup.+ -type polysilicon gate layer with reference to a correction table for the pattern adjacent to the n.sup.+ -type polysilicon gate layer. After that, a p.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the p.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be an n.sup.+ -type polysilicon gate layer, thereby correcting the size of the p.sup.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: May 9, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Hisako Aoyama, Soichi Inoue, Kazuko Yamamoto, Sachiko Kobayashi
  • Patent number: 6004701
    Abstract: In a Levenson photomask design method of partially forming a plurality of opening patterns for passing incident light in a light-shielding film for shielding the incident light, and arranging, on some patterns, phase shifters, line segment pairs of different patterns which are adjacent to each other within a predetermined distance R are extracted in units of line segments obtained by dividing the patterns. A pattern within a predetermined distance S from the central point of the opposite region of a line segment pair of interest in a direction perpendicular to the line segments is obtained. The obtained pattern is subjected to a process simulation to obtain resolution easiness representing the easiness in resolving the adjacent patterns. On the basis of the resolution easiness obtained for the adjacent pattern pair within the distance R, a phase shifter is arranged in ascending order of resolution easiness to give a phase difference.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: December 21, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taiga Uno, Kiyomi Koyama, Kazuko Yamamoto, Satoshi Tanaka, Sachiko Kobayashi, Koji Hashimoto