Abstract: According to one embodiment, a memory device includes: a first layer stack including first insulating layers arranged in a first direction and spaced apart from one another; second and third layer stacks, each including conductive layers spaced apart from one another and provided at levels of layers identical to the first insulating layers, respectively, and being spaced apart from each other; a memory pillar extending in the first direction in the third layer stack, a portion of the memory pillar intersecting each of the conductive layers functioning as a memory cell; a first member in contact with the first and second layer stacks between the first and second layer stacks and extending in a second direction; and a second member in contact with the second and third layer stacks between the second and third layer stacks and extending in the second direction.

Abstract: In general, according to one embodiment, a stress analysis method comprising: dividing a surface of an object into a plurality of first rectangles each having a first size, on data; and acquiring a first type value for each of the first rectangles. The method further includes: specifying, from among the first rectangles, a plurality of second rectangles that have the first type value of a magnitude that falls within a first range and form a rectangle; and generating a stress model for a set of the second rectangles by using the second rectangles as an element.

Abstract: A semiconductor device according to an embodiment includes a substrate, a transistor, an insulating layer, and a first sealing portion. The substrate includes a first region, and a second region provided to surround an outer periphery of the first region. The transistor is provided on the substrate in the first region. The insulating layer is provided above the transistor and over the first region and the second region. The first sealing portion is provided to divide the insulating layer and surround the outer periphery of the first region in the second region. The first sealing portion includes a first void.

Abstract: According to one embodiment, a semiconductor device includes a first substrate, a second substrate joined to the first substrate. A first region of the semiconductor device that includes a peripheral circuit is between the first substrate and the second substrate. A second region that includes a memory cell array is between the first region and the second substrate. A layer that is embedded in the second substrate has a Young's modulus that is higher than that of silicon and/or an internal stress that is higher than that of silicon oxide.

Abstract: A semiconductor storage device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked along a stacking direction, and a plurality of first pillars extending in the stacked body along the stacking direction to form memory cells at intersections with at least some of the plurality of conductive layers. The stacked body includes a stair portion in which the plurality of conductive layers are stacked in a stepped manner at a position separated from the plurality of first pillars in a first direction intersecting the stacking direction. At least a lowermost insulating layer of the plurality of insulating layers has at least one bending portion bent in the stacking direction at an end of the plurality of conductive layers in the stair portion along the first direction.

Abstract: In general, according to one embodiment, a stress analysis method comprising: dividing a surface of an object into a plurality of first rectangles each having a first size, on data; and acquiring a first type value for each of the first rectangles. The method further includes: specifying, from among the first rectangles, a plurality of second rectangles that have the first type value of a magnitude that falls within a first range and form a rectangle; and generating a stress model for a set of the second rectangles by using the second rectangles as an element.

Abstract: A semiconductor memory device of an embodiment includes a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner, a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion, and a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, in which a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where memory cells are arranged.

Abstract: According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.

Abstract: A semiconductor memory device of an embodiment includes a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner, a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion, and a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, in which a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where memory cells are arranged.

Abstract: According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a plurality of columnar portions, a separation portion, and a wall portion. The separation portion extends through the stacked body in a first direction and separates the stacked body into a plurality of blocks in a second direction. The separation portion includes a conductive material contacting the substrate. The wall portion is disposed between the separation portion and a columnar portion of the plurality of columnar portions most proximal to the separation portion. The wall portion pierces a lowermost electrode layer of the plurality of electrode layers and pierces an interface between the substrate and the stacked body.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a plurality of columnar portions, a separation portion, and a wall portion. The separation portion extends through the stacked body in a first direction and separates the stacked body into a plurality of blocks in a second direction. The separation portion includes a conductive material contacting the substrate. The wall portion is disposed between the separation portion and a columnar portion of the plurality of columnar portions most proximal to the separation portion. The wall portion pierces a lowermost electrode layer of the plurality of electrode layers and pierces an interface between the substrate and the stacked body.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a circuit portion, a stacked body, at least one columnar member, a device isolation portion, and at least one first support member. The columnar member is in contact with an interconnect layer, and includes a contact extending in a stacking direction of a plurality of electrode films in the stacked body. The device isolation portion is provided in the stacked body and extends in a first direction and the stacking direction. The first support member is provided in the stacked body, extends in the stacking direction, and is located on the device isolation portion in a second direction crossing the first direction and along the upper surface of the substrate.

Abstract: According to an embodiment, a semiconductor device includes a substrate, a stacked body, and a second insulating film. A first insulating film and an electrode film are alternately stacked in the stacked body so as to extend in a first direction along an upper surface of the substrate. The stacked body includes an end portion in the first direction, a shape of the end portion being a staircase shape. The second insulating film is provided in first and second regions, the end portion being provided in the first region, the second region being contiguous to the first region in the first direction. The second insulating film includes a part in which a width of a second direction in the second region is smaller than a width of the second direction in the first region, the second direction crossing the first direction and along the upper surface of the substrate.

Abstract: According to an embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film, a first structure body, and a first connection portion. The stacked body includes a first conductive layer and a second conductive layer. The semiconductor pillar extends in the first direction through the stacked body. The memory film provides between the stacked body and the semiconductor pillar. The first conductive layer includes a first region and a second region. The first region does not overlap the second conductive layer in the first direction. The second region overlaps the second conductive layer in the first direction. The first structure body extends in the first direction through the first region to a position of a front surface of the first region. The first connection portion is electrically connected to the first conductive layer.

Abstract: According to one embodiment, a gas supply member is provided with a gas supply passage including a gas flow channel with a first diameter, and an exhaust port connected to one end portion of the gas flow channel and provided to a surface of a downstream side of the gas supply member. An yttria-containing film is formed on a surface constituting the exhaust port and the surface of the downstream side of the gas supply member. At least a part of the surface constituting the exhaust port is formed with a curved surface.

Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, a first magnetoresistive element provided on the substrate. A second magnetoresistive element which is provided on the substrate and is arranged next to the first magnetoresistive element. Each of the first and second magnetoresistive elements includes a first magnetic layer, a tunnel barrier layer and a second magnetic layer. The tunnel barrier layer is provided on the first magnetic layer, the second magnetic layer is provided on the tunnel barrier layer. A first stress member having a tensile stress as an internal stress is provided on an area including a side face of the stacked body.

Abstract: According to one embodiment, a semiconductor device includes a memory cell, a dummy gate electrode and an interlayer insulation film. The memory cell includes a plurality of word lines as an arrangement on a semiconductor substrate and apart from each other, and a selection transistor being apart from an end of the arrangement. The dummy gate electrode has a structure larger than a word line in the arrangement direction, and is arranged between the end of the arrangement and the selection transistor. The interlayer insulation film is existed above a region including the word line, the dummy gate electrode and the selection transistor, and between the neighboring word lines, the dummy gate electrode and the selection transistor, and has a cavity between the neighboring word lines.

Abstract: According to one embodiment, a gas supply member is provided with a gas supply passage including a gas flow channel with a first diameter, and an exhaust port connected to one end portion of the gas flow channel and provided to a surface of a downstream side of the gas supply member. An yttria-containing film is formed on a surface constituting the exhaust port and the surface of the downstream side of the gas supply member. At least a part of the surface constituting the exhaust port is formed with a curved surface.

Abstract: A solid-state image pickup apparatus includes an image pickup pixel unit in which a plurality of pixels each including a photoelectric conversion element and a field-effect transistor are arranged on a semiconductor substrate so that a light-receiving surface is disposed at a first surface side of the semiconductor substrate; a peripheral circuit unit provided at a periphery of the image pickup pixel unit of the semiconductor substrate; and a multilayered wiring layer in which a plurality of wiring layers for driving the field-effect transistor of the image pickup pixel unit are laminated at a second surface side of the semiconductor substrate, wherein a wiring in each of the wiring layers constituting the multilayered wiring layer is disposed so that a coverage of the wiring located at least in the image pickup pixel unit of the semiconductor substrate reaches 100%, viewed from the second surface side.