Abstract: A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

Abstract: A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.

Abstract: A solid-state image pickup apparatus includes an image pickup pixel unit in which a plurality of pixels each including a photoelectric conversion element and a field-effect transistor are arranged on a semiconductor substrate so that a light-receiving surface is disposed at a first surface side of the semiconductor substrate; a peripheral circuit unit provided at a periphery of the image pickup pixel unit of the semiconductor substrate; and a multilayered wiring layer in which a plurality of wiring layers for driving the field-effect transistor of the image pickup pixel unit are laminated at a second surface side of the semiconductor substrate, wherein a wiring in each of the wiring layers constituting the multilayered wiring layer is disposed so that a coverage of the wiring located at least in the image pickup pixel unit of the semiconductor substrate reaches 100%, viewed from the second surface side.

Abstract: A semiconductor device includes an effective wire formed above a substrate in a multilayer interconnection structure and having a first electrode pad in a top layer; a first reinforcing material formed in the multilayer interconnection structure like surrounding the effective wire; a protective film configured to protect a final surface of the multilayer interconnection structure; and a second reinforcing material formed at a position in contact with the protective film and also between an area in which the effective wire is formed and a chip area end, the second reinforcing material being constituted by a film pattern whose Young's modulus is larger than that of a conductor constituting the first electrode pad and that of a conductor constituting the first reinforcing material.

Abstract: A semiconductor device includes an effective wire formed above a substrate in a multilayer interconnection structure and having a first electrode pad in a top layer; a first reinforcing material formed in the multilayer interconnection structure like surrounding the effective wire; a protective film configured to protect a final surface of the multilayer interconnection structure; and a second reinforcing material formed at a position in contact with the protective film and also between an area in which the effective wire is formed and a chip area end, the second reinforcing material being constituted by a film pattern whose Young's modulus is larger than that of a conductor constituting the first electrode pad and that of a conductor constituting the first reinforcing material.

Abstract: A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.

Abstract: A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.

Abstract: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a plated film on a substrate which has a recessed portion on its surface so as to bury in the recessed portion by a plating method; forming over the plated film a compressive stress-applying film which is composed of a material having a thermal expansion coefficient of 60% or less compared with a thermal expansion coefficient of a metal composing the plated film; heat-treating while applying a compressive stress to the plated film by the compressive stress-applying film; and removing the compressive stress-applying film and the plated film which is not buried in the recessed portion.

Abstract: A semiconductor device is disclosed, which includes at least two layers superposed on each other in a stacking direction above a substrate, each of the layers including an insulating film a conductive layer films, a conductive plug electrically connected to the conductive layer, and at least one dummy via chain provided in the insulating films and stacked in the at least two layers, wherein the dummy via chain includes at least two reinforcing metal layers and at least one reinforcing plug.

Abstract: There is disclosed a semiconductor device comprising a plurality of inter-level dielectric films which are stacked and provided in plural layers above a substrate, at least one first conductor which is provided in at least one inter-level dielectric film of the stacked inter-level dielectric films, and a plurality of second conductors which are provided in the inter-level dielectric film in which the first conductor is provided and which are connected to the lower surface of the first conductor and which are extended along the downward direction from the first conductor and further extended along a first direction and a second direction perpendicular to the first direction in such a manner as to be spaced apart from each other to form a lattice shape.

Abstract: A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

Abstract: A semiconductor device is disclosed, which includes at least two layers superposed on each other in a stacking direction above a substrate, each of the layers including an insulating film a conductive layer films, a conductive plug electrically connected to the conductive layer, and at least one dummy via chain provided in the insulating films and stacked in the at least two layers, wherein the dummy via chain includes at least two reinforcing metal layers and at least one reinforcing plug.

Abstract: A semiconductor device includes an insulating film whose relative dielectric constant is 3.4 or less, at least one conductive layer, at least one conductive plug which is electrically connected to the conductive layer to form a conduction path, at least one reinforcing material whose Young's modulus is 30 GPa or more, at least one first reinforcing plug which is connected to the conductive layer and which is formed in contact with the reinforcing material, a reinforcing metal layer which is provided in the insulating film in an area other than that where the conductive layer is formed, and which is electrically disconnected from the conductive layer and the conductive plug, and a second reinforcing plug which is connected to the under side of the reinforcing metal layer and which is formed in contact with the reinforcing material.

Abstract: There is disclosed a semiconductor device comprising a plurality of inter-level dielectric films which are stacked and provided in plural layers above a substrate, at least one first conductor which is provided in at least one inter-level dielectric film of the stacked inter-level dielectric films, and a plurality of second conductors which are provided in the inter-level dielectric film in which the first conductor is provided and which are connected to the lower surface of the first conductor and which are extended along the downward direction from the first conductor and further extended along a first direction and a second direction perpendicular to the first direction in such a manner as to be spaced apart from each other to form a lattice shape.

Abstract: A semiconductor device comprising a first insulating layer formed above a semiconductor substrate, and comprising a first insulating material, a second insulating material and a hole, a relative dielectric constant of the first insulating material being 3 or less, a Young's modulus of the first insulating material being 10 GPa or less, a linear expansivity of the first insulating material being greater than 30×10?6° C.?1, and a linear expansivity of the second insulating material being 30×10?6° C.?1 or less, and a second insulating layer formed on the first insulating layer, the second insulating layer having a groove connected to the hole, wherein a linear expansivity ? of the first insulating layer within 6 ?m from the hole is 30×10?6° C.?1 or less, where ? = ? i = 1 ? v i ? ? i , vi and ?i are a volume ratio and a linear expansivity of an i-th insulating material.

Abstract: A photomask comprises a substrate, a translucent film selectively formed on the substrate, and a shading film selectively formed on the translucent film, wherein when the substrate, the translucent film and the shading film have Young's moduli (MPa) E0 E1 and E2, and film thickness (m) d0, d1 and d2 respectively, internal stresses (MPa) of the translucent film and the shading film at room temperature are s1 and s2 respectively, a covering rate by the translucent film defined by an area in which the shading film is not formed is expressed as h, and coefficients are expressed as k1=1.3×10?8, k2=?9.5×10?2, k3=6.0×10?7, and k4=?5.2×10?2 respectively, the substrate, the translucent film and the shading film satisfy a condition given by the following expression: ? 1 E 0 · d 0 · { h · ( k 1 · S 1 E 1 · d 1 + k 2 ) + ( k 3 · S 2 E 2 · d 2 + k 4 ) } ? ? 1.4 × 10 - 4 ? ( m - 1 ) .

Abstract: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a plated film on a substrate which has a recessed portion on its surface so as to bury in the recessed portion by a plating method; forming over the plated film a compressive stress-applying film which is composed of a material having a thermal expansion coefficient of 60% or less compared with a thermal expansion coefficient of a metal composing the plated film; heat-treating while applying a compressive stress to the plated film by the compressive stress-applying film; and removing the compressive stress-applying film and the plated film which is not buried in the recessed portion.

Abstract: A semiconductor device includes a semiconductor substrate on which an element is formed, a low dielectric constant insulation film formed over the semiconductor substrate and having a relative dielectric constant of 3 or lower, a plug and a wiring layer buried in the low dielectric constant insulation film, and a high Young's modulus insulation film having a Young's modulus of 15 GPa or higher and formed in contact with a side of the plug between the low dielectric constant insulation film and the plug.

Abstract: A semiconductor device includes an insulating film whose relative dielectric constant is 3.4 or less, at least one conductive layer, at least one conductive plug which is electrically connected to the conductive layer to form a conduction path, at least one reinforcing material whose Young's modulus is 30 GPa or more, at least one first reinforcing plug which is connected to the conductive layer and which is formed in contact with the reinforcing material, a reinforcing metal layer which is provided in the insulating film in an area other than that where the conductive layer is formed, and which is electrically disconnected from the conductive layer and the conductive plug, and a second reinforcing plug which is connected to the under side of the reinforcing metal layer and which is formed in contact with the reinforcing material.

Abstract: There is disclosed a semiconductor device comprising an insulating film which is provided in at least one layer above a substrate and whose relative dielectric constant is 3.4 or less, at least one conductive layer provided in the insulating film, at least one conductive plug which is formed in the insulating film and which is electrically connected to the conductive layer to form a conduction path, at least one reinforcing material which is provided under at least the conductive layer and whose Young's modulus is 30 GPa or more, and at least one first reinforcing plug which is connected to the conductive layer and which is formed in contact with the reinforcing material.