Patents by Inventor Sadamichi Takakusaki
Sadamichi Takakusaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7957158Abstract: A circuit device having improved packaging density is provided. A circuit device of the present invention includes: a circuit board having its surface covered with an insulating layer; conductive patterns formed on a surface of the insulating layer; circuit elements electrically connected to the conductive patterns; and leads connected to pads formed of the conductive patterns. Furthermore, a control element is fixed to an upper surface of a land part formed of a part of a lead, and a back surface of the land part is spaced apart from an upper surface of the circuit board.Type: GrantFiled: October 30, 2007Date of Patent: June 7, 2011Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Katsuyoshi Mino
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Publication number: 20110121335Abstract: Provided are a light emitting module and a manufacturing method thereof, the light emitting module having improved heat radiation properties and improved adhesion between a sealing resin for sealing a light emitting element and other members. A light emitting module 10 includes: a metal substrate 12; a concave part 18 provided by partially denting an upper surface of the metal substrate 12; a light emitting element 20 accommodated in the concave part 18; and a sealing resin 32 covering the light emitting element 20. A convex part 11 is further provided on the upper surface of the metal substrate 40 in a region thereof surrounding the concave part 18. The sealing resin 32 is allowed to adhere to the convex part 11, thereby improving adhesion strength between the sealing resin 32 and the metal substrate 12.Type: ApplicationFiled: August 28, 2008Publication date: May 26, 2011Applicants: SANYO Electric Co., Inc., SANYO Semiconductor Co., Ltd., SANYO Consumer Electronics Co., Ltd.Inventors: Sadamichi Takakusaki, Tatsuya Motoike, Akihisa Matsumoto
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Patent number: 7936569Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.Type: GrantFiled: January 30, 2006Date of Patent: May 3, 2011Assignee: Sanyo Electric Co., Ltd.Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
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Patent number: 7851921Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer.Type: GrantFiled: July 30, 2007Date of Patent: December 14, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Mayumi Nakasato, Hideki Mizuhara, Takaya Kusabe, Sadamichi Takakusaki
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Publication number: 20100299920Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer.Type: ApplicationFiled: August 13, 2010Publication date: December 2, 2010Applicant: Sanyo Electric Co., Ltd.Inventors: Mayumi Nakasato, Hideki Mizuhara, Takaya Kusabe, Sadamichi Takakusaki
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Patent number: 7714232Abstract: Provided are a hybrid integrated circuit device in which fine patterns can be formed while current-carrying capacitances are ensured, and a method of manufacturing the same. The hybrid integrated circuit device of the present invention includes conductive patterns formed on a front surface of a circuit substrate and circuit elements electrically connected respectively to the conductive patterns. The conductive patterns include a first conductive pattern and a second conductive pattern formed more thickly than the first conductive pattern. The second conductive pattern includes a protruding portion protruding in a thickness direction thereof.Type: GrantFiled: February 18, 2005Date of Patent: May 11, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Yusuke Igarashi, Sadamichi Takakusaki, Motoichi Nezu, Takaya Kusabe
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Publication number: 20090166895Abstract: A semiconductor device that includes a metal substrate including a top surface, a bottom surface and four side surfaces, a conductive pattern insulated from the metal substrate, and a semiconductor element mounted on and electrically connected to the conductive pattern. The top surface is insulated. Each of the side surfaces of the metal substrate includes a first inclining side surface and a second inclining side surface so as to form a convex shape protruding outwardly between the top surface and the bottom surface of the metal substrate, and the first inclining side surfaces of a pair of two opposing side surfaces are smaller than corresponding first inclining side surfaces of another pair of two opposing side surfaces.Type: ApplicationFiled: December 23, 2008Publication date: July 2, 2009Applicants: SANYO Electric Co., Ltd.Inventors: Mitsuru NOGUCHI, Sadamichi Takakusaki
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Publication number: 20090135572Abstract: Provided is a circuit device in which an electronic circuit to be incorporated therein operates stably. A hybrid integrated circuit device includes multiple circuit boards which are disposed on approximately the same plane. An electronic circuit including a conductive pattern and a circuit element is formed on each top surface of the circuit boards. Furthermore, these circuit boards are integrally supported by a sealing resin. Moreover, a lead connected to the electronic circuit formed on the surface of the circuit board is led out from the sealing resin to the outside.Type: ApplicationFiled: August 30, 2006Publication date: May 28, 2009Applicant: Sanyo Electric Co., Ltd.Inventors: Sadamichi Takakusaki, Noriaki Sakamoto
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Publication number: 20090129038Abstract: Provided is a simplified structure of a circuit device in which a power element generating a large amount of heat is incorporated. The circuit device according to the present invention includes: a circuit board whose surface is covered with an insulating layer; a conductive pattern formed on the surface of the insulating layer; a circuit element electrically connected to the conductive pattern; and a lead connected to a pad formed of the conductive pattern. Furthermore, a power element is fixed to the top surface of a land portion formed of a part of the lead. Accordingly, the land portion serves as a heat sink, thereby contributing to heat dissipation.Type: ApplicationFiled: August 30, 2006Publication date: May 21, 2009Applicant: SANYO ELECTRIC CO., LTDInventors: Sadamichi Takakusaki, Noriaki Sakamoto
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Patent number: 7521290Abstract: The method of the present invention includes a first step of preparing a substrate in which a plurality of circuit boards are integrally connected to one another, each of the circuit boards having conductive patterns which include pads formed on a surface of the circuit board; a second step of electrically connecting circuit elements to the respective conductive patterns on each of the circuit boards; a third step of positioning ends of leads above the respective pads by superposing a lead frame including the plurality of leads on the substrate, and fixing the leads to the pads; and a fourth step of separating the circuit boards from the substrate in a state where the leads are fixed to the respective pads on each of the circuit boards, and thus separating the leads from the lead frame.Type: GrantFiled: January 11, 2007Date of Patent: April 21, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Sadamichi Takakusaki, Noriaki Sakamoto
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Publication number: 20090078455Abstract: Provided are: a light emitting module which has an improved heat-dissipating property and whose reflectance reduction is prevented. The light emitting module mainly includes: a metal substrate; a conductive pattern formed on the upper surface of the metal substrate; and a light emitting element disposed on the upper surface of the metal substrate and electrically connected to the conductive pattern. Furthermore, in the light emitting module, an insulating layer is removed in a region where the conductive pattern is not formed, but is left unremoved in a region right below (or covered with) the conductive pattern. In other words, in the region where the conductive pattern is not formed, the upper surface of the metal substrate is not covered with the conductive pattern, and a metal material constituting the metal substrate is exposed.Type: ApplicationFiled: September 25, 2008Publication date: March 26, 2009Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd., SANYO Consumer Electronics Co., Ltd.Inventors: Sadamichi Takakusaki, Koichiro Ono, Akihisa Matsumoto
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Publication number: 20080123299Abstract: A circuit device exhibiting excellent heat radiation properties and a manufacturing method thereof are hereby provided. A circuit device comprises a circuit board, an insulating layer formed on the circuit board, a conductive pattern formed on the insulating layer, a circuit element electrically connected to the conductive pattern, wherein a protrusion partially extending and being buried in the insulating layer is provided on the circuit board. Accordingly, heat generated inside the device can be efficiently discharged to the exterior via the protrusion.Type: ApplicationFiled: March 24, 2005Publication date: May 29, 2008Inventors: Sadamichi Takakusaki, Yusuke Igarashi, Motoichi Nezu, Takaya Kusabe
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Publication number: 20080119065Abstract: A circuit device having improved packaging density is provided. A circuit device of the present invention includes: a circuit board having its surface covered with an insulating layer; conductive patterns formed on a surface of the insulating layer; circuit elements electrically connected to the conductive patterns; and leads connected to pads formed of the conductive patterns. Furthermore, a control element is fixed to an upper surface of a land part formed of a part of a lead, and a back surface of the land part is spaced apart from an upper surface of the circuit board.Type: ApplicationFiled: October 30, 2007Publication date: May 22, 2008Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.Inventors: Sadamichi TAKAKUSAKI, Noriaki SAKAMOTO, Katsuyoshi MINO
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Publication number: 20080106875Abstract: Provided are a hybrid integrated circuit device in which fine patterns can be formed while current-carrying capacitances are ensured, and a method of manufacturing the same. The hybrid integrated circuit device of the present invention includes conductive patterns formed on a front surface of a circuit substrate and circuit elements electrically connected respectively to the conductive patterns. The conductive patterns include a first conductive pattern and a second conductive pattern formed more thickly than the first conductive pattern. The second conductive pattern includes a protruding portion protruding in a thickness direction thereof.Type: ApplicationFiled: February 18, 2005Publication date: May 8, 2008Inventors: Yusuke Igarashi, Sadamichi Takakusaki, Motoichi Nezu, Takaya Kusabe
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Publication number: 20080023841Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer.Type: ApplicationFiled: July 30, 2007Publication date: January 31, 2008Applicant: SANYO ELECTRIC CO., LTD.Inventors: Mayumi Nakasato, Hideki Mizuhara, Takaya Kusabe, Sadamichi Takakusaki
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Publication number: 20070221704Abstract: A method of manufacturing a circuit device of the present invention comprises the steps of: forming a conductive pattern including a first pad and a second pad on the surface of a substrate; applying a solder paste to the surface of the first pad and then thermally melting the solder paste, thus forming solder; fixing a circuit element to the second pad; and fixing a circuit element to the first pad with the solder therebetween. Furthermore, a flux constituting the solder paste contains sulfur. Since the sulfur is mixed into the solder paste, surface tension of the solder paste is lowered; accordingly occurrence of sink is suppressed.Type: ApplicationFiled: January 30, 2006Publication date: September 27, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
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Publication number: 20070205017Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.Type: ApplicationFiled: January 30, 2006Publication date: September 6, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
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Publication number: 20070193027Abstract: The method of the present invention includes a first step of preparing a substrate in which a plurality of circuit boards are integrally connected to one another, each of the circuit boards having conductive patterns which include pads formed on a surface of the circuit board; a second step of electrically connecting circuit elements to the respective conductive patterns on each of the circuit boards; a third step of positioning ends of leads above the respective pads by superposing a lead frame including the plurality of leads on the substrate, and fixing the leads to the pads; and a fourth step of separating the circuit boards from the substrate in a state where the leads are fixed to the respective pads on each of the circuit boards, and thus separating the leads from the lead frame.Type: ApplicationFiled: January 11, 2007Publication date: August 23, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Sadamichi Takakusaki, Noriaki Sakamoto
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Patent number: 7250352Abstract: In preferred embodiments, a method of manufacturing a hybrid integrated circuit device is provided, in which a plurality of circuit substrates 10 are manufactured from a single metal substrate 10A? by dicing. In some embodiments, the method includes: preparing a metal substrate 10A? having an insulating layer 11 formed on the top surface thereof; forming a plurality of conductive patterns 12 on the top surface of insulating layer 11; forming grooves 20 in lattice form on the rear surface of metal substrate 10B?; mounting hybrid integrated circuits onto conductive patterns 12; and separating individual circuit substrates 10 with, for example, a rotatable cutter.Type: GrantFiled: April 24, 2003Date of Patent: July 31, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Masahiko Mizutani, Sadamichi Takakusaki, Motoichi Nezu, Kazutoshi Motegi, Mitsuru Noguchi
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Patent number: 7221049Abstract: A circuit device having a multilayered wiring structure and an excellent heat dissipation property, and a method of manufacturing the circuit device are provided. In a circuit device, a multilayered wiring structure including a first conductive pattern and a second conductive pattern is formed on a surface of a circuit substrate. A first insulating layer is formed entirely on the surface of the circuit substrate. The first conductive pattern and the second conductive pattern are mutually insulated by a second insulating layer. An amount and grain sizes of filler included in the second insulating layer are smaller than an amount and grain sizes of filler included in the first insulating layer. Therefore, it is easier to connect the above two conductive patterns by way of penetrating the second insulating layer.Type: GrantFiled: May 27, 2005Date of Patent: May 22, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Yusuke Igarashi, Sadamichi Takakusaki, Hideki Mizuhara, Ryosuke Usui