Patents by Inventor Sadamichi Takakusaki

Sadamichi Takakusaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7186921
    Abstract: A circuit device which enables formation of a minute pattern while securing a current capacity and has excellent heat release properties, and a manufacturing method thereof are provided. In a circuit device of the present invention, among multiple wiring layers, a first wiring layer is formed of a thin first conductive pattern and a thick second conductive pattern. Therefore, formation of the minute patterns is realized while securing the current capacity. Moreover, a small-signal circuit element is mounted on the first conductive pattern, and a large-current circuit element is mounted on the second conductive pattern. Thus, circuit elements having different sizes of currents to be handled are mounted on the same board. Furthermore, heat release properties are improved by the second conductive pattern which is formed to be thick.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: March 6, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Sadamichi Takakusaki
  • Patent number: 7163841
    Abstract: To provide a method of manufacturing a highly reliable circuit device realizing a smaller, thinner and lighter configuration. In the method of manufacturing a circuit device according to the invention, a resin sealed body is separated from a supporting substrate, after the resin sealed body containing a circuit device is formed on a top surface of the supporting substrate. Therefore, manufacture of a circuit device having no substrate becomes possible and it realizes a thinner and lighter circuit device with improved heat dissipation. Moreover, since sealing with a sealing resin can be performed on the supporting substrate, warps, caused by the differences in thermal expansion coefficients between the sealing resin and conductive patterns and between the sealing resin and circuit components, can be prevented.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: January 16, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takakusaki, Yusuke Igarashi, Motoichi Nezu, Takaya Kusabe
  • Publication number: 20060024862
    Abstract: To provide a method of manufacturing a highly reliable circuit device realizing a smaller, thinner and lighter configuration. In the method of manufacturing a circuit device according to the invention, a resin sealed body is separated from a supporting substrate, after the resin sealed body containing a circuit device is formed on a top surface of the supporting substrate. Therefore, manufacture of a circuit device having no substrate becomes possible and it realizes a thinner and lighter circuit device with improved heat dissipation. Moreover, since sealing with a sealing resin can be performed on the supporting substrate, warps, caused by the differences in thermal expansion coefficients between the sealing resin and conductive patterns and between the sealing resin and circuit components, can be prevented.
    Type: Application
    Filed: July 11, 2005
    Publication date: February 2, 2006
    Inventors: Sadamichi Takakusaki, Yusuke Igarashi, Motoichi Nezu, Takaya Kusabe
  • Publication number: 20050263320
    Abstract: A circuit device which enables formation of a minute pattern while securing a current capacity and has excellent heat release properties, and a manufacturing method thereof are provided. In a circuit device of the present invention, among multiple wiring layers, a first wiring layer is formed of a thin first conductive pattern and a thick second conductive pattern. Therefore, formation of the minute patterns is realized while securing the current capacity. Moreover, a small-signal circuit element is mounted on the first conductive pattern, and a large-current circuit element is mounted on the second conductive pattern. Thus, circuit elements having different sizes of currents to be handled are mounted on the same board. Furthermore, heat release properties are improved by the second conductive pattern which is formed to be thick.
    Type: Application
    Filed: May 31, 2005
    Publication date: December 1, 2005
    Inventors: Yusuke Igarashi, Sadamichi Takakusaki
  • Publication number: 20050263482
    Abstract: In a method of manufacturing a circuit device of the present invention, protruding portions protruding upward are formed in part of a conductive pattern formed on the front surface of a circuit substrate. Next, the front surface of the circuit substrate including the protruding portions is coated with coating resin. Subsequently, the coating resin is etched so that the top surfaces of the protruding portions are exposed. Then, the fixation and electrical connection of circuit elements are performed. Finally, an electric circuit formed on the front surface is sealed, whereby a hybrid integrated circuit device is completed.
    Type: Application
    Filed: May 27, 2005
    Publication date: December 1, 2005
    Inventors: Sadamichi Takakusaki, Motoichi Nezu, Takaya Kusabe
  • Publication number: 20050263880
    Abstract: A circuit device having a multilayered wiring structure and an excellent heat dissipation property, and a method of manufacturing the circuit device are provided. In a circuit device, a multilayered wiring structure including a first conductive pattern and a second conductive pattern is formed on a surface of a circuit substrate. A first insulating layer is formed entirely on the surface of the circuit substrate. The first conductive pattern and the second conductive pattern are mutually insulated by a second insulating layer. An amount and grain sizes of filler included in the second insulating layer are smaller than an amount and grain sizes of filler included in the first insulating layer. Therefore, it is easier to connect the above two conductive patterns by way of penetrating the second insulating layer.
    Type: Application
    Filed: May 27, 2005
    Publication date: December 1, 2005
    Inventors: Yusuke Igarashi, Sadamichi Takakusaki, Hideki Mizuhara, Ryosuke Usui
  • Patent number: 6956252
    Abstract: In preferred embodiments, a compact a hybrid integrated circuit device 1 can be provided. A conductive pattern 12 is formed on the top surface of a circuit substrate 10, on the top surface of which an insulating layer 11 has been provided. Conductive pattern 12 is formed over the entirety of the top surface of the circuit substrate. Specifically, conductive pattern 12 is also formed at parts within 2 mm from the peripheral ends of circuit substrate 10. Also, a heat sink 13A or other circuit element 13 with some height can be positioned near a peripheral end part of circuit substrate 10. By arranging hybrid integrated circuit device 1, the degree of integration of hybrid integrated circuit is improved. Thus, in a case where the same circuit as a prior-art example is formed, the size of the entire hybrid integrated circuit device can be made small.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: October 18, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masahiko Mizutani, Sadamichi Takakusaki, Motoichi Nezu, Kazutoshi Motegi
  • Publication number: 20040014270
    Abstract: In preferred embodiments, a compact a hybrid integrated circuit device 1 can be provided. A conductive pattern 12 is formed on the top surface of a circuit substrate 10, on the top surface of which an insulating layer 11 has been provided. Conductive pattern 12 is formed over the entirety of the top surface of the circuit substrate. Specifically, conductive pattern 12 is also formed at parts within 2 mm from the peripheral ends of circuit substrate 10. Also, a heat sink 13 A or other circuit element 13 with some height can be positioned near a peripheral end part of circuit substrate 10. By arranging hybrid integrated circuit device 1, the degree of integration of hybrid integrated circuit is improved. Thus, in a case where the same circuit as a prior-art example is formed, the size of the entire hybrid integrated circuit device can be made small.
    Type: Application
    Filed: April 24, 2003
    Publication date: January 22, 2004
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Masahiko Mizutani, Sadamichi Takakusaki, Motoichi Nezu, Kazutoshi Motegi
  • Publication number: 20030232489
    Abstract: In preferred embodiments, a method of manufacturing a hybrid integrated circuit device is provided, in which a plurality of circuit substrates 10 are manufactured from a single metal substrate 10A′ by dicing. In some embodiments, the method includes: preparing a metal substrate 10A′ having an insulating layer 11 formed on the top surface thereof; forming a plurality of conductive patterns 12 on the top surface of insulating layer 11; forming grooves 20 in lattice form on the rear surface of metal substrate 10B′; mounting hybrid integrated circuits onto conductive patterns 12; and separating individual circuit substrates 10 with, for example, a rotatable cutter.
    Type: Application
    Filed: April 24, 2003
    Publication date: December 18, 2003
    Inventors: Masahiko Mizutani, Sadamichi Takakusaki, Motoichi Nezu, Kazutoshi Motegi, Mitsuru Noguchi