Abstract: A hard disk drive system including a controller and a plurality of slave testing modules located in respective components of the hard disk drive system. The controller is arranged on a printed circuit board of the hard disk drive system and is configured to transmit information from the hard disk drive system to a host device, receive information from the host device, and, using a master testing module located in the controller, provide test configuration data corresponding to the information received from the host device. Each of the plurality of slave testing modules is configured to receive the test configuration data from the master testing module and test operation of the respective component of the hard disk drive system using the test configuration data.

Abstract: A system for tracking the use of medication by a user in real-time generates data pertaining to the medication use including time of consumption and amount of medication available, and transmit the data to a network so the data is readily accessible to at least one party of interest. The system includes a base unit housing affixed to a cover for use with a medication container, the base unit housing having a micro-electro-mechanical system able to detect motion of the cover and determine when the user removes the cover from the medication container, a computing device to generate the medication use data based on information from the micro-electro-mechanical system, and a communication system to transmit the medication use data to a cloud computer via the network, thereby providing the at least one party of interest access to the cloud computer and the medication use data.

Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.

Abstract: A system for measuring and recording data pertaining to a user's vital signs in response to a single action by the user is provided. The system includes a base unit with a computer system, metallic layers affixed to a first side face and a bottom face of the base unit, an aperture, and a flexible shaft extending from the bottom face of the base, and an extension member pivotably mounted to a second side face of the base unit. The system receives the user's thumb on the metallic layer located on the first side face, index finger between the base unit and the extension member, lips on the bottom face metallic layer and tongue above the flexible shaft to capture the vital signs data and communicate the data to the remote location.

Abstract: A memory module including a first memory, a second memory, a test module, and a control module. The first memory is configured to store pages of data to be tested for errors. The second memory is configured to store addresses for the pages of data and store copies of the pages of data. The test module is configured to perform testing on the pages of data stored in the first memory. The control module is configured to, prior to the testing being performed by the test module on the pages of data stored in the first memory, cause the second memory to store the addresses and the copies of the pages of data stored in the first memory and, subsequent to the testing being performed by the test module, store the copies of the pages of data to the first memory based on the addresses stored in the second memory.

Abstract: A system for controlling a storage device. A semiconductor chip of the storage device, includes a first memory. The first memory corresponds to a first type of memory, is configured to perform random access memory functions, and is not configured to perform direct memory access functions. A second memory external to the semiconductor chip is configured to interface with the semiconductor chip. The second memory corresponds to a second type of memory that is different than the first type of memory, is configured to perform direct memory access functions, and is not configured to perform random access memory function. The second memory includes a memory cell and an interface configured to interface between components of the second memory including the memory cell and the semiconductor chip.

Abstract: A memory system comprising a first memory, a control module, a test module, and a second memory. The first memory is configured to store pages of data to be tested. The control module is configured to store identifiers of the pages of data. The test module is configured to test the pages of data in the first memory. The second memory is configured to, while the pages of data stored in the first memory are being tested, store the identifiers of the pages of data and store the pages of data. The control module is further configured to, after the test module completes testing of the pages of data in the first memory, move the pages of data from the second memory to the first memory based on the identifiers of the pages of data.

Abstract: A system for testing an integrated circuit, in which the system includes a deserializer, a frame sync module, and a diagnostic module. The deserializer is external to the integrated circuit and is configured to receive messages in a serial data format, wherein the messages include test results associated with the integrated circuit, and deserialize the messages into data frames. The frame sync module is configured to provide control code based on the data frames, wherein the control code includes, in a digital format, status information associated with the messages deserialized into the data frames. The diagnostic module is configured to generate, based on the control code, diagnostic data associated with states of the integrated circuit.

Abstract: A printed circuit board of a hard disk drive system includes a first component and a plurality of second components of the hard disk drive system. The first component is configured to transmit information to, and receive information from, a host device via a communication interface of the printed circuit board. The first component includes a first testing module operating as a master testing module. Each of the plurality of second components includes a respective second testing module operating as a slave testing module. The first component is connected to each of the plurality of second components and is configured to provide test configuration data to each of the respective second testing modules. The test configuration data corresponds to the information received from the host device, and the test configuration data enables each of the respective second testing modules to test operation of the plurality of second components.

Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.

Abstract: A golf club that can automatically align the club head with intended path of ball direction. The golf club encompasses a movable club head, electronics, a power source and motor driver for adjusting golf club head position at time of impact with a golf ball. The golf club can also serve as teaching aid for tracking a golfer swing path and errors in golf club path.

Abstract: A method, system, and a computer-readable medium for pairing a wireless sensor device to a user are disclosed. The method, system, and computer-readable medium comprise providing an identification code that includes a network address within the wireless sensor device. The method, system, and computer-readable medium include utilizing an application within a mobile device. The application selects the user, obtains the identification code, scans for network addresses, and compares the network address to the scanned network addresses. When the network address matches one of the scanned network addresses, the wireless sensor device is paired to the user by the application.

Abstract: A health-monitoring system and method are disclosed. The health-monitoring system and method comprise a sensory system and a sensory to front-end communication (SFCM) protocol coupled to the sensory system. The health-monitoring system and method include a front-end system coupled to the sensory system and a front-end to back-end communication (FBCM) protocol coupled to the front-end system. The health-monitoring system and method include a back-end system. The SFCM protocol communicates with the front-end system using a first state awareness link and the FBCM protocol communicates with the back-end system using a second state awareness link.

Abstract: In memory devices that degrade with use, a memory controller may monitor and record a usage history of portions of the memory. The memory controller can then vary a strength of error correction coding to protect information written to various portions of the memory having different usage histories. More specifically, and memory can receive information to be stored in the memory, select a portion of memory to store the information, and store the information in the selected portion of the memory with an error correction coding having a strength that is based on a usage history of the selected portion of the memory.

Abstract: In one or more embodiments, an integrated circuit includes a programmable memory, a key generation module and a module. The programmable memory is to maintain a first key portion. The key generation module is to generate a key using the first key portion from the programmable memory and a second key portion received via a memory interface. The module is to encrypt or decrypt data using the key.

Abstract: A system includes a first integrated circuit. The first integrated circuit includes a direct memory access (DMA) circuit, a first random access memory (RAM) that is accessed by the DMA circuit using DMA, a data/command terminal that communicates with the DMA circuit and that receives a selection signal, and an M-bit data terminal that communicates with the DMA circuit and that receives a write command during a first period when the selection signal has a first state, a write address during a second period when the selection signal has a second state that is different than the first state, and write data during T third periods when the selection signal has the second state. M is an integer greater than one and T is an integer greater than zero. The first period, the second period, and the T third periods are non-overlapping.

Abstract: A system including an interface and a plurality of solder joint testing modules. The interface is configured to receive test configuration data to configure each of a plurality of integrated system test (IST) modules. Each of the plurality of solder joint testing modules is configured to, based on the test configuration data, i) apply a pulse having a predetermined amplitude and width to a solder joint associated with a respective one of the plurality of IST modules, ii) monitor a resultant waveform that is generated in response to the pulse, and iii) determine an integrity of the solder joint in response to the resultant waveform. Each of the plurality of solder joint testing modules and the respective ones of the plurality of IST modules are located on a same system on chip (SOC).

Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.

Abstract: A memory circuit including a logic circuit, content addressable memory, and a multiplexer. The logic circuit is configured to output a first address. The content addressable memory is configured to i) receive the first address and ii) output a substitute address and a match signal if the first address matches a second address stored in the content addressable memory. The multiplexer is configured to i) receive the first address and the substitute address and ii) selectively output one of the first address and the substitute address based on the match signal.

Abstract: A system receives serial messages from a device under test. The system includes a deserializer configured to i) receive the serial messages and, ii) based on the serial messages, form data frames. A frame sync module is configured to form Joint Task Action Group (JTAG) data bits based on the data frames. A plurality of virtual JTAG test access ports are configured to i) receive the JTAG data bits and ii) shift the JTAG data bits between the plurality of virtual JTAG test access ports.