Abstract: An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the first deserializer and interprets the test instructions and data using the first format. A frame capture module receives test results according to the interpreted test instructions and data. A first control module communicates with the frame capture module and generates first format control data. The frame capture module packages the test results and the first format control data into frames. A first serializer serializes the frames.

Abstract: An integrated circuit (IC) comprises an embedded processor. An embedded in-circuit emulator (ICE) emulates at least one function of the embedded processor, performs at least one of testing and debugging on the IC, and generates testing results based on the at least one of the testing and the debugging. A serializer located on the IC receives the testing results from at least one of the embedded ICE and the embedded processor, serializes the testing results, and serially outputs the testing results from the IC.

Abstract: In memory devices that degrade with use, a memory controller may monitor and record a usage history of portions of the memory. The memory controller can then vary a strength of error correction coding to protect information written to various portions of the memory having different usage histories. More specifically, and memory can receive information to be stored in the memory, select a portion of memory to store the information, and store the information in the selected portion of the memory with an error correction coding having a strength that is based on a usage history of the selected portion of the memory.

Abstract: A memory storage device connectable to a bus comprises a first memory module that stores data, a second memory module that is capable of being programmed, and a memory controller that communicates with the first memory module, the second memory module, and the bus, and that determines an address mapping of selected areas of the first memory module onto the second memory module. When the memory controller receives an access request from the bus, the memory controller accesses data from the first memory module unless the address mapping specifies that the access request maps to the second memory module, whereupon the memory controller accesses replacement data from the second memory module.

Abstract: An interface that communicates with first and second interface modules, an analyzer and an integrated circuit comprises a first path from the first and second interface modules and the analyzer to the integrated circuit. The first path includes a first serializer that serializes at least one of first control data and/or test data from at least one of the first and/or second interface modules. A second path from the integrated circuit to the first and second interface modules and the analyzer includes a high speed deserializer that deserializes serial data containing at least one of test result data and/or second control data from the integrated circuit. A frame sync module synchronizes data from the high speed deserializer to identify frames. The high speed deserializer outputs the second control data to at least one of the first and/or second interface modules. The frame sync module outputs the frames to the analyzer.

Abstract: A system is provided that retrieves test information from a target integrated circuit. A serializer receives the test information in a first format and divides and reformats the test information into first and second serial messages. The serializer is located on the target integrated circuit and has a first serial output that sends the first serial message and a second serial output that sends the second serial message. A deserializer communicates with the first and second serial outputs and receives the first and second serial messages. The deserializer retrieves a first portion of the test information from the first serial message, a second portion of the test information from the second serial message, and reconstructs the test information from the first portion and the second portion.

Abstract: A system for testing a target integrated circuit comprises a host device that executes a debugging and testing analysis program, that transmits test instructions and data to the integrated circuit and that analyzes received data from the target integrated circuit. A first interface module communicates with the host device and formats the test instructions and data using a first format. A first serializer serializes the test instructions and data. A first deserializer on the target integrated circuit communicates with the first serializer and deserializes the test instructions and data. A control module on the target integrated circuit communicates with the first deserializer, interprets the test instructions and data using the first format. A testing module receives the interpreted test instructions and data from the control module and performs testing and debugging of the target integrated circuit.

Abstract: A hard disk drive system comprises N hard disk drive means for performing hard disk drive functions and is connected in a daisy chain, wherein N is greater than one. The system includes integrated system test (IST) means for testing and that is integrated with a first one of the N hard disk drive means and includes pattern generating means for generating test pattern data and pattern monitoring means for receiving a returned test pattern. The pattern generating means generates test pattern data that is routed from the first one of the N hard disk drive means serially through the remaining ones of the N hard disk drive means and back to the first one of the N hard disk drive means. The pattern monitoring means generates test result data based on returned test data returned to the first one of the N hard disk drive means.

Abstract: A memory architecture for a disk drive system in which Synchronous Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two memory components are provided to improve performance of the system, as well as reduce pin count and cost. An integrated circuit memory includes a random-access memory. The random-access memory includes a first terminal for receiving selection information. The random-access memory includes a second terminal for selectively (i) receiving a command, or (ii) receiving or transmitting data in accordance with the selection information received by the first terminal.

Abstract: A computer program is stored on a computer-readable medium and executed by a processor and performs a method of transmitting and receiving signals between a hard disk controller and a read channel. The computer program comprises transmitting a data gate signal; transmitting or receiving data under control of the data gate signal; transmitting a media gate signal; and transmitting mode selection information under control of the media gate signal, wherein said data gate signal controls the transfer of data between the hard disk controller and the read channel and wherein data is transferred between a storage media and the read channel in accordance with the media gate signal.

Abstract: A data storage device architecture includes a HDA printed circuit board (PCB) including a spindle motor driver, a read/write arm driver, a read channel driver, and a first input/output (I/O) interface that are arranged on the HDA PCB. An application PCB includes at least one of an application specific integrated circuit and a processor that performs application and hard drive control related processing. A buffer stores application and hard drive control related data. A hard drive controller (HDC), a mapping driver, and a second I/O interface are arranged on the application PCB. The second I/O interface communicates with the first I/O interface. The mapping driver is capable of at least one of mapping logical addresses to physical addresses and monitoring a location of a read/write head.

Abstract: A hard disk drive system comprises an interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. A system on chip (SOC) includes integrated system test (IST) modules. A memory module communicates with the SOC and includes memory and an IST module. One of the IST modules communicates with the interface and is a master IST module that receives the test configuration data and that configures others of the IST modules for testing a component of the hard disk drive system.

Abstract: A system on chip (SOC), comprises an external interface that receives test configuration data, transmits test result data, and that transmits and receives application data. A plurality of SOC components, each including an integrated system test (IST) module, wherein at least one of the SOC components includes a controller that communicates with the external interface. At least one of the plurality of SOC components communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing the plurality of SOC components.

Abstract: A hard disk drive system includes an external interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. The hard disk drive system includes a system on chip (SOC) that includes a controller and a read/write channel that communicates with the controller and that includes an integrated system test (IST) module that communicates with the external interface. A memory module communicates with the SOC and includes memory and an IST module. The hard disk drive system includes a spindle/voice coil motor driver module that includes an IST module. At least one of the IST modules is a master IST module that receives the test configuration data and that configures the IST modules for testing at least one of the controller, the read/write channel, and the memory module.

Abstract: A system comprises a printed circuit board (PCB). A system on chip (SOC) mounted on the PCB includes a controller that communicates with an external interface that receives test configuration data, transmits test result data, and transmits and receives application data. At least one chip mounted to the PCB, wherein the SOC comprises an SOC component that includes an integrated system test (IST) module. At least one chip comprises a chip component that includes an integrated system test (IST) module. At least one of the SOC component and the chip component, communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing at least one of the SOC component and the chip component.

Abstract: A memory system comprises first memory that includes memory cells that are selectively refreshed at a refresh rate. A test module tests operation of the memory cells at the refresh rate and that identifies T of the memory cells that are inoperable when refreshed at the refresh rate, where T is an integer greater than zero. Content addressable memory (CAM) includes D CAM memory cells where D is an integer greater than or equal to one. An adaptive refresh module selectively adjusts a refresh rate of the first memory based on T and D.

Abstract: A memory module comprises first memory that stores data in memory blocks; second memory that temporarily stores data from at least one of the memory blocks and third memory for storing a relationship between addresses of the at least one of the memory blocks in the first memory and corresponding addresses of the data from the at least one of the memory blocks in the second memory. Storage capacities of the second and third memories are less than a storage capacity of the first memory. A control module selectively transfers data in the at least one of the memory blocks in the first memory to the second memory and stores and retrieves data from the second memory for the at least one of the memory blocks based on the relationship during the testing.

Abstract: A memory system comprises first memory that includes memory cells. Content addressable memory (CAM) includes CAM memory cells, stores addresses of selected ones of the memory cells, stores data having the addresses in corresponding ones of the CAM memory cells and retrieves data having the addresses from corresponding ones of the CAM memory cells. An adaptive refresh module stores data from selected ones of the memory cells in the CAM memory cells to one of increase and maintain a time period between refreshing of the memory cells.

Abstract: A memory module comprises first memory that includes memory blocks, second memory, and non-volatile memory. A control module, during testing of at least one of the memory blocks having a first address, stores data from the at least one of the memory blocks in the second memory at a second address and stores the first and second addresses in the non-volatile memory. Content addressable memory (CAM) stores addresses of defective memory locations in the first memory and stores and retrieves data for the defective memory locations.

Abstract: An integrated circuit which utilizes a serial trace output interface instead of the known parallel trace output interface for transferring test data from the integrated circuit, thereby reducing the number of pins needed for outputting test data. Specifically, a preferred embodiment of the present invention uses a serializer/deserializer (SERDES) interface which captures output testing data in frames, serializes the framed data, and outputs the serialized data on at least one pin. The output serialized data is deserialized, and the deserialized data is synchronized in order to find the frame boundaries. The synchronized frames are then unpacked to retrieve the original testing data. Another preferred embodiment of the present invention uses a bi-directional SERDES both for inputting testing and debugging instructions and data from the analysis software and for outputting testing and debugging results and data to the analysis software.