Abstract: A concrete or mortar composition including (i) a cementitious binder material that contains Portland cement and 1-50 wt % date palm ash relative to the total weight of the cementitious binder material, (ii) a coarse aggregate, (iii) a fine aggregate, and (iv) water, wherein the cementitious binder material is present at 200-500 kg per m3 of the concrete or mortar composition.

Abstract: A concrete or mortar composition including (i) a cementitious binder material that contains Portland cement and 1-50 wt % date palm ash relative to the total weight of the cementitious binder material, (ii) a coarse aggregate, (iii) a fine aggregate, and (iv) water, wherein the cementitious binder material is present at 200-500 kg per m3 of the concrete or mortar composition.

Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Abstract: A position sensor comprises a waveguide of a magnetostrictive material, which extends along a measurement path and which is configured for conducting mechanical pulses triggered by magnetostriction, and a housing for the waveguide. A positioning element is provided which is elastic at least regionally; which is held in the housing while being deformed; and which has a recess which extends along the measurement path and forms a receiver for the waveguide. In the position sensor in accordance with the invention, the recess has a slit which extends along the measurement path; which, viewed in a cross-sectional plane, reaches from a reception section up to a boundary of the positioning element; and which enables a lateral insertion of the waveguide into the reception section. The invention furthermore comprises a method of manufacturing a position sensor in accordance with the invention.

Abstract: A position sensor comprises a waveguide of magnetostrictive material which extends along a measurement path and which is configured for conducting mechanical pulses triggered by magnetostriction. A transducer at a first end of the waveguide serves for coupling a current pulse into the waveguide and for detecting a mechanical pulse conducted by the waveguide in the direction of the transducer. A damping element of an elastomer material is provided at a second end of the waveguide for damping a mechanical pulse propagating in the direction of the second end, wherein the hardness of the elastomer material increases as the distance from the transducer increases. The invention furthermore relates to a method of manufacturing a damping element of such a position sensor.

Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Abstract: Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.

Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Abstract: The invention relates to a compact thermal reactor for rapid growth of high quality carbon nanotubes (CNT2) produced by chemical process with low power consumption comprising: a processing chamber having a vacuum vessel, the vacuum vessel having a side cover formed of a first side wall and a second side wall, a top cover, a bottom cover connected to a support stand; feed through housing provided with a substrate; a heating system consisting of a heating element and back means; and at least one each inlet and outlet for gas injection into the process chamber for growing high quality carbon nanotubes over the substrate.

Abstract: An electronic device which can easily access information associated with an item displayed in a notification bar and a method for operating a notification bar thereof are provided. The electronic device includes a touch screen for detecting a selection of an item displayed in the notification bar, and a controller for controlling the touch screen so as to display an information providing window which provides information associated with the selected item, in response to selection of the item.

Abstract: The invention relates to a process of making ammonia gas indicator, using single wall carbon nanotubes (SWCNTs)/alumina (Al2O3) composite thick film, comprising the steps of (a) preparing a nanoporous SWCNTs/Al2O3 composite thick film of thickness in the range of 60 to 65?m prepared by sol-gel process; (b) curing the film at a temperature in the range of 450° C. to 500° C. for a time period in the range 0.5 to 2 hour to obtain a cured sample; (c) providing thick film planar electrodes of Ag—Pd paste on same side of the cured sample by screen printing; and (d) heat treating the resultant cured sample with electrodes at a temperature in the range of 800° C. to 850° C. for a time period in the range of 0.5 to 2 hours to obtain a gas indicator.

Abstract: A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.

Abstract: A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.

Abstract: An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained.

Abstract: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

Abstract: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch.