Patents by Inventor Saiful Islam
Saiful Islam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7663963Abstract: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.Type: GrantFiled: June 6, 2008Date of Patent: February 16, 2010Assignee: International Business Machines CorporationInventors: Sam Gat-Shang Chu, Maureen Anne Delaney, Saiful Islam, Dung Quoc Nguyen, Jafar Nahidi
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Publication number: 20090251974Abstract: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch.Type: ApplicationFiled: April 7, 2008Publication date: October 8, 2009Applicant: International Business Machines CorporationInventors: Sam Gat-Shang Chu, Saiful Islam, Jae-Joon Kim, Stephen V. Kosonocky
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Patent number: 7545176Abstract: An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.Type: GrantFiled: October 25, 2007Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Vikas Agarwal, Sanjay Dubey, Saiful Islam, Gaurav Mittal
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Publication number: 20090108920Abstract: An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.Type: ApplicationFiled: October 25, 2007Publication date: April 30, 2009Inventors: Vikas Agarwal, Sanjay Dubey, Saiful Islam, Gaurav Mittal
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Publication number: 20090010077Abstract: A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.Type: ApplicationFiled: July 2, 2007Publication date: January 8, 2009Inventors: Vikas Agarwal, Sam Gat-Shang Chu, Saiful Islam, Philip George Shephard, III
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Patent number: 7474574Abstract: A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.Type: GrantFiled: July 2, 2007Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Vikas Agarwal, Sam Gat-Shang Chu, Saiful Islam, Philip George Shephard, III
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Publication number: 20080279015Abstract: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.Type: ApplicationFiled: July 26, 2008Publication date: November 13, 2008Applicant: International Business Machines CorporationInventors: Sam Gat-Shang Chu, Saiful Islam, Shelton Siuwah Leung, Jose Angel Paredes
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Patent number: 7443737Abstract: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.Type: GrantFiled: March 11, 2004Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: Sam Gat-Shang Chu, Saiful Islam, Shelton Siuwah Leung, Jose Angel Paredes
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Publication number: 20080251888Abstract: An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Applicant: IBM CorporationInventors: Vikas Agarwal, Asit S. Ambekar, Sanjay Dubey, Saiful Islam
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Publication number: 20080239860Abstract: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.Type: ApplicationFiled: June 6, 2008Publication date: October 2, 2008Applicant: International Business Machines CorporationInventors: Sam Gat-Shang Chu, Maureen Anne Delaney, Saiful Islam, Dung Quoc Nguyen, Jafar Nahidi
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Patent number: 7400548Abstract: Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. A mechanism to write the consecutive entries by only having a 4 to 16 decode of one address is also provided. In addition, a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address is provided. The two read word lines are used to access the two read ports of the entries in the sub-arrays.Type: GrantFiled: February 9, 2005Date of Patent: July 15, 2008Assignee: International Business Machines CorporationInventors: Sam Gat-Shang Chu, Maureen Anne Delaney, Saiful Islam, Dung Quoc Nguyen, Jafar Nahidi
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Publication number: 20080095203Abstract: A technique for reducing speckle in a projected image includes forming an image using a plurality of laser light emitters. An input to the plurality of laser light emitters is non-mechanically perturbed to a degree sufficient to disrupt wavefront uniformity across the array of laser light emitters.Type: ApplicationFiled: October 19, 2006Publication date: April 24, 2008Inventors: Alexandre M. Bratkovski, Shih-Yuan Wang, M. Saiful Islam
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Patent number: 7243209Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.Type: GrantFiled: January 27, 2005Date of Patent: July 10, 2007Assignee: International Business Machines CorporationInventors: Sam Gat-Shang Chu, Maureen Anne Delaney, Saiful Islam, Jafar Nahidi, Dung Quoc Nguyen
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Patent number: 7243170Abstract: An instruction buffer and a method of buffering instructions.Type: GrantFiled: November 24, 2003Date of Patent: July 10, 2007Assignee: International Business Machines CorporationInventors: Taqi N. Buti, Brian W. Curran, Maureen A. Delaney, Saiful Islam, Zakaria M. Khwaja, Jafar Nahidi, Dung Q. Nguyen
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Patent number: 7205941Abstract: A composite material and related methods are described, the composite material being configured to exhibit a negative effective permittivity and/or a negative effective permeability for incident radiation at an operating wavelength, the composite material comprising an arrangement of electromagnetically reactive cells of small dimension relative to the operating wavelength. Each cell includes an externally powered gain element for enhancing a resonant response of that cell to the incident radiation at the operating wavelength.Type: GrantFiled: August 30, 2004Date of Patent: April 17, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Shih-Yuan Wang, Philip J Kuekes, Wei Wu, Joseph Straznicky, M. Saiful Islam
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Publication number: 20060179257Abstract: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.Type: ApplicationFiled: February 9, 2005Publication date: August 10, 2006Inventors: Sam Chu, Maureen Delaney, Saiful Islam, Dung Nguyen, Jafar Nahidi
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Publication number: 20060171208Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.Type: ApplicationFiled: January 27, 2005Publication date: August 3, 2006Inventors: Sam Chu, Maureen Delaney, Saiful Islam, Jafar Nahidi, Dung Nguyen
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Publication number: 20050216698Abstract: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.Type: ApplicationFiled: March 11, 2004Publication date: September 29, 2005Applicant: International Business Machines CorporationInventors: Sam Chu, Saiful Islam, Shelton Leung, Jose Paredes
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Publication number: 20050114603Abstract: An instruction buffer and a method of buffering instructions.Type: ApplicationFiled: November 24, 2003Publication date: May 26, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Taqi Buti, Brian Curran, Maureen Delaney, Saiful Islam, Zakaria Khwaja, Jafar Nahidi, Dung Nguyen