Patents by Inventor Sailesh Kumar

Sailesh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9130856
    Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: September 8, 2015
    Assignee: NetSpeed Systems
    Inventors: Sailesh Kumar, Eric Norige, Joji Philip, Mahmud Hassan, Sundari Mitra, Joseph Rowlands
  • Publication number: 20150236963
    Abstract: The present disclosure is directed to Quality of Service (QoS) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a Network on Chip (NoC) for an endpoint agent. The QoS policy and handshake protocols may involve the use of credits for buffer allocation which are sent to agents in the NoC to compel the acceptance of data and the allocation of an appropriate buffer. Messages sent to the agent may also have a priority associated with the message, wherein higher priority messages have automatic bandwidth allocation and lower priority messages are processed using a handshake protocol.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 20, 2015
    Applicant: NETSPEED SYSTEMS
    Inventor: Sailesh KUMAR
  • Patent number: 9076009
    Abstract: Techniques to provide a secure, shared personal map layer include determining a geographic location. The geographic location is associated with operation of a device. The techniques also include determining indication that describes a relationship between the geographic location and a first user of the device. The techniques also include determining a privacy level for the indication. Then, the first user of the device is associated with the indication and the geographic location and the privacy level. In some embodiments, the techniques also include determining a personal description vocabulary word based, at least in part, on the geographic location and a context for the device. Then it is determined to present on the device a prompt that includes the personal description vocabulary word.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: July 7, 2015
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Sailesh Kumar Sathish, Jilei Tian
  • Publication number: 20150188847
    Abstract: Systems and methods described herein are directed to streaming bridge design implementations that help interconnect and transfer transaction packets between multiple source and destination host interfaces through a Network on Chip (NoC) interconnect, which includes a plurality of NoC router layers and virtual channels (VCs) connecting the router layers. Implementations are configured to support a variety of different traffic profiles, each having a different set of traffic flows. Streaming bridge design implementation can divide streaming bridge into a streaming TX bridge and a streaming RX bridge, wherein TX bridge is operatively coupled with host TX interfaces and RX bridge is operatively coupled with host RX interfaces, and where TX bridge forwards transaction packets from host TX interfaces to different router layers/VCs of NoC, and RX bridge, on the other hand, receives packets from NoC router layers/VCs and transmits the packets to host RX interfaces based on Quality of Service.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 2, 2015
    Applicant: NETSPEED SYSTEMS
    Inventors: Rajesh CHOPRA, Sailesh KUMAR
  • Publication number: 20150186277
    Abstract: The present application is directed to designing a NoC interconnect architecture by a means of specification, which can indicate implementation parameters of the NoC including, but not limited to, number of NoC agent interfaces, and number of cache coherency controllers. Flexible identification of NoC agent interfaces and cache coherency controllers allows for an arbitrary number of agents to be associated with the NoC upon configuring the NoC from the specification.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 2, 2015
    Applicant: NETSPEED SYSTEMS
    Inventors: Joe ROWLANDS, Sailesh KUMAR
  • Publication number: 20150178435
    Abstract: Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 25, 2015
    Applicant: NETSPEED SYSTEMS
    Inventor: Sailesh KUMAR
  • Patent number: 9054977
    Abstract: Example implementations described herein are directed to automatically determine an optimal NoC topology using heuristic based optimizations. First, an optimal orientation of ports of various hosts is determined based on the system traffic and connectivity specification. Second, the NoC routers to which the host's port are directly connected to are determined in the NoC layout. Third, an optimal set of routes are computed for the system traffic and the required routers and channels along the routes are allocated forming the full NoC topology. The three techniques can be applied in any combination to determine NoC topology, host port orientation, and router connectivity that reduces load on various NoC channels and improves latency, performance, and message transmission efficiency between the hosts.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: June 9, 2015
    Assignee: NetSpeed Systems
    Inventors: Sailesh Kumar, Amit Patankar, Eric Norige
  • Patent number: 9042397
    Abstract: An apparatus comprising a chip comprising a plurality of nodes, wherein a first node from among the plurality of nodes is configured to receive a first flit comprising a first timestamp, receive a second flit comprising a second timestamp, determine whether the first flit is older than the second flit based on the first timestamp and the second timestamp, transmit the first flit before the second flit if the first flit is older than the second flit, and transmit the second flit before the first flit if the first flit is not older than the second flit.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: May 26, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventors: Rohit Sunkam Ramanujam, Sailesh Kumar, William Lynch
  • Publication number: 20150143050
    Abstract: The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: Netspeed Systems
    Inventors: Joe ROWLANDS, Sailesh KUMAR
  • Publication number: 20150117261
    Abstract: The present application is directed to designing an efficient Network on Chip (NoC) interconnect architecture that is adaptable to varied interface protocols of different SoC components/hosts and is compliant to handle different types and models of traffic profiles. Aspects of the present application include a method, which may involve utilizing multiple traffic profiles described in a specification to generate a NoC that satisfies all the traffic profiles. Such a NoC interconnect architecture can be formed from multiple traffic profiles by generating a single consolidated traffic profile from individual or subset based dependency graphs of the multiple traffic profiles.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Applicant: NETSPEED SYSTEMS
    Inventor: Sailesh KUMAR
  • Patent number: 9015292
    Abstract: An apparatus for providing distribution of composite capability information for devices within a distributed network may include at least one processor and at least one memory including computer program code. The memory and the computer program code may be configured to, with the processor, cause the apparatus at least to receive local capability information from a participant device in a distributed network in which the local capability information describes the capabilities of the participant device, combine the local capability information from the participant device with other capability information defining capabilities of other participant devices to produce composite capability information, generate differential information indicating differences between the local capability information and the composite capability information, and provide the differential information to the participant device. A corresponding method and computer program product are also provided.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: April 21, 2015
    Assignee: Nokia Corporation
    Inventor: Sailesh Kumar Sathish
  • Publication number: 20150103822
    Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that support a variety of different component protocols each having different sets of data and/or metadata even after the NoC is designed and finalized. Example implementations include, automatically changing format of packets received from an originating SoC component by an originating bridge based on a NoC interface protocol and then transmitting the packet across the NoC interconnect to a destination bridge. The format may again be changed based on the protocol of the destination SoC component. The proposed protocol can be configured to map various transactions presented to it, be they packets belonging to the physical, data link layer, network layer or transport layer. As part of the mapping process, virtual channels for latency or deadlock avoidance may be created and may be maintained for the entire life of the packet within the NoC.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: NETSPEED SYSTEMS
    Inventors: Jaya GIANCHANDANI, Sailesh KUMAR, Eric NORIGE, Joe ROWLANDS, Rajesh CHOPRA
  • Patent number: 9009648
    Abstract: Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: April 14, 2015
    Assignee: NetSpeed Systems
    Inventors: Sailesh Kumar, Eric Norige, Joji Philip, Mahmud Hassan, Sundari Mitra, Joseph Rowlands
  • Patent number: 9007920
    Abstract: Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: April 14, 2015
    Assignee: NetSpeed Systems
    Inventors: Sailesh Kumar, Eric Norige, Joji Philip, Mahmud Hassan, Sundari Mitra, Joseph Rowlands
  • Publication number: 20150052309
    Abstract: Addition, search, and performance of other allied activities relating to keys are performed in a hardware hash table. Further, high performance and efficient design may be provided for a hash table applicable to CPU caches and cache coherence directories. Set-associative tables and cuckoo hashing are combined for construction of a directory table of a directory based cache coherence controller. A method may allow configuration of C cuckoo ways, where C is an integer greater than or equal to 2, wherein each cuckoo way Ci is a set-associative table with N sets, where each set has an associativity of A, where A is an integer greater than or equal to 2.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: NETSPEED SYSTEMS
    Inventors: Joji PHILIP, Sailesh KUMAR, Joe ROWLANDS
  • Publication number: 20150043575
    Abstract: Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the NoC during routing towards the destination components indicated in the message. Example implementations further relate to an efficient way of implementing multicast in any given NoC topology, wherein one or more multicast trees in the given NoC topology are formed and one of these trees are used for routing a multicast message to its intended destination components mentioned therein.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Applicant: NetSpeed Systems
    Inventors: Sailesh KUMAR, Eric NORIGE, Joe ROWLANDS, Joji PHILIP
  • Publication number: 20150036536
    Abstract: Example implementations described herein are directed to automatically determine an optimal NoC topology using heuristic based optimizations. First, an optimal orientation of ports of various hosts is determined based on the system traffic and connectivity specification. Second, the NoC routers to which the host's port are directly connected to are determined in the NoC layout. Third, an optimal set of routes are computed for the system traffic and the required routers and channels along the routes are allocated forming the full NoC topology. The three techniques can be applied in any combination to determine NoC topology, host port orientation, and router connectivity that reduces load on various NoC channels and improves latency, performance, and message transmission efficiency between the hosts.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicant: NETSPEED SYSTEMS
    Inventors: Sailesh KUMAR, Amit PATANKAR, Eric NORIGE
  • Publication number: 20150032437
    Abstract: Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 29, 2015
    Applicant: NETSPEED SYSTEMS
    Inventors: Sailesh KUMAR, Amit PATANKAR, Eric NORIGE
  • Publication number: 20150016257
    Abstract: Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve automatically generating internal dependency specification of a system component based on dependencies between incoming/input and outgoing/output interface channels of the component. Dependencies between incoming and outgoing interface channels of the component can be determined by blocking one or more outgoing interface channels and evaluating impact of the blocked outgoing channels on the incoming interface channels. Another implementation described herein involves determining inter-component communication dependencies by measuring impact of a deadlock on the blocked incoming interface channels of one or more components to identify whether a dependency cycle is formed by blocked incoming interface channels.
    Type: Application
    Filed: August 26, 2013
    Publication date: January 15, 2015
    Applicant: NETSPEED SYSTEMS
    Inventors: Sailesh KUMAR, Eric NORIGE, Joji PHILIP, Joseph ROWLANDS
  • Patent number: 8934377
    Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that supports reconfigurability to support a variety of different traffic profiles each having different sets of traffic flows after the NoC is designed and deployed in a SoC. Reconfiguration of the NoC to map and load a new traffic profile or change the currently mapped traffic profile is performed by an external optimization module which maps various transactions of a given traffic profile to the NoC and reconfigure the NoC hardware by loading the computed mapping information. As part of the mapping process, load balancing between NoC layers may be performed by automatically assigning the transactions in the traffic profile to be routed over certain NoC layers and channels, automatically determining the routes based on the bandwidth requirements of the transaction. The deadlock avoidance and isolation properties of various transactions are maintained during the mapping.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 13, 2015
    Assignee: NetSpeed Systems
    Inventors: Sailesh Kumar, Eric Norige