Patents by Inventor Sailesh Kumar

Sailesh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8930618
    Abstract: An apparatus comprising a storage device comprising a plurality of memory tiles each comprising a memory block and a processing element, and an interconnection network coupled to the storage device and configured to interconnect the memory tiles, wherein the processing elements are configured to perform at least one packet processing feature, and wherein the interconnection network is configured to promote communication between the memory tiles. Also disclosed is a network component comprising a receiver configured to receive network data, a logic unit configured to convert the network data for suitable deterministic memory caching and processing, a serial input/output (I/O) interface configured to forward the converted network data in a serialized manner, a memory comprising a plurality of memory tiles configured to store and process the converted network data from the serial I/O interface, and a transmitter configured to forward the processed network data from the serial I/O interface.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: January 6, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventors: Sailesh Kumar, William Lynch
  • Publication number: 20140376569
    Abstract: Example implementations described herein are directed to a micro-architecture of NoC router clocking which allows for a flexible Globally Asynchronous Locally Synchronous (GALS) implementation. The example implementations allow arbitrary clock domain partitions to be defined across the system. The example implementations further involve allowing the components of the NoC to be configured by the user through a NoC generation system to achieve the desired arbitrary clock domain partitioning.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Joji PHILIP, Joseph ROWLANDS, Sailesh KUMAR
  • Patent number: 8885510
    Abstract: Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: November 11, 2014
    Assignee: NetSpeed Systems
    Inventors: Sailesh Kumar, Joji Philip, Eric Norige, Mahmud Hassan, Sundari Mitra
  • Publication number: 20140328172
    Abstract: Systems and methods described herein are directed to solutions for NoC interconnects that provide congestion avoidance and end-to-end uniform and weighted-fair allocation of resource bandwidths among various contenders in a mesh or torus interconnect. The example implementations are fully distributed and involve using explicit congestion notification messages or local congestion identification for congestion detection. Based on the congestion level detected, the injection rates of traffic at various agents are regulated that avoids congestion and also provides end-to-end QoS. Alternative example implementations may also utilize end-to-end credit based flow control between communicating agents for resource and bandwidth allocation of the destination between the contending sources. The resource allocation is performed so that both the weighted and strict bandwidth allocation QoS policies are satisfied.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Inventors: Sailesh KUMAR, Eric NORIGE
  • Publication number: 20140331027
    Abstract: A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links
    Type: Application
    Filed: July 17, 2014
    Publication date: November 6, 2014
    Inventors: Joji Philip, Sailesh Kumar, Eric Norige, Mahmud Hassan, Sundari Mitra
  • Publication number: 20140328208
    Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Inventors: Eric NORIGE, Sailesh KUMAR
  • Patent number: 8880554
    Abstract: An apparatus comprising a storage device comprising a hash table including a plurality of buckets, each bucket being capable of storing at least one data item, and a processor configured to apply at least a first and a second hash function upon receiving a key to generate a first index and a second index, respectively, the first and second indices identifying first and second potential buckets in the hash table for storing a new data item associated with the key, determine whether at least one of the first and second potential buckets have space available to store the new data item, and responsive to determining that at least one of the first and second potential buckets have available space, insert the new data item into one of the first or second potential buckets determined to have available space.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: November 4, 2014
    Assignee: Futurewei Technologies, Inc.
    Inventors: Sailesh Kumar, Zhenxiao Liu, William Lynch
  • Publication number: 20140301241
    Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the topology of different NoC layers and maps system traffic flows to various routes in various NoC layers that satisfies the latency requirements of the flows. The number of layers and their topology is dynamically allocated and optimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers and updating the topology of the NoC layers as they are mapped. In addition to allocating additional NoC layers and topologies to satisfy the latency requirements of the flows, the NoC layers and topologies may also be allocated to satisfy the bandwidth requirements of the flows or to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various flows.
    Type: Application
    Filed: April 4, 2013
    Publication date: October 9, 2014
    Applicant: NETSPEED SYSTEMS
    Inventors: Sailesh KUMAR, Eric NORIGE
  • Publication number: 20140298358
    Abstract: An approach is provided for providing an optimization framework for task-oriented event execution. A planner platform processes and/or facilitates a processing of user indication information to determine an event associated with a device, a user of the device, or a combination thereof. The planner platform further causes, at least in part, a creation of a planner object specifying, at least in part, one or more processes related to the event, one or more triggers for the one or more processes, or a combination thereof. The planner platform also causes, at least in part, an execution of the one or more processes at the device, one or more other devices, or a combination thereof based, at least in part, on a monitoring of contextual information against the one or more triggers.
    Type: Application
    Filed: December 14, 2011
    Publication date: October 2, 2014
    Inventors: Jilei Tian, Sailesh Kumar Sathish
  • Publication number: 20140254388
    Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that supports reconfigurability to support a variety of different traffic profiles each having different sets of traffic flows after the NoC is designed and deployed in a SoC. Reconfiguration of the NoC to map and load a new traffic profile or change the currently mapped traffic profile is performed by an external optimization module which maps various transactions of a given traffic profile to the NoC and reconfigure the NoC hardware by loading the computed mapping information. As part of the mapping process, load balancing between NoC layers may be performed by automatically assigning the transactions in the traffic profile to be routed over certain NoC layers and channels, automatically determining the routes based on the bandwidth requirements of the transaction. The deadlock avoidance and isolation properties of various transactions are maintained during the mapping.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Inventors: Sailesh KUMAR, Eric NORIGE
  • Patent number: 8819616
    Abstract: Example implementations described herein are directed to a system on chip (SoC) that can include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality of routers, and a plurality of links between routers. The plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip (NoC) architecture with a sparse mesh topology. The sparse mesh topology involves a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed. The plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 26, 2014
    Assignee: NetSpeed Systems
    Inventors: Joji Philip, Sailesh Kumar, Eric Norige, Mahmud Hassan, Sundari Mitra
  • Patent number: 8819611
    Abstract: Example implementations described herein are directed to a floor plan for a Network on Chip (NoC) topology that can include a plurality of on chip blocks of substantially non-uniform shapes and dimensions. An interconnection network is synthesized along with a plan for a physical layout of the interconnection network based on physical dimensions of the plurality of on chip blocks, the physical dimensions of the floorplan and relative placement information for placing the plurality of on chip blocks on the floorplan. Porosity information for the plurality of on chip blocks on the floorplan and required chip functionality may also be taken into consideration.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 26, 2014
    Assignee: NetSpeed Systems
    Inventors: Joji Philip, Sailesh Kumar, Eric Norige, Mahmud Hassan, Sundari Mitra
  • Patent number: 8812499
    Abstract: An approach for sharing and/or viewing one or more remixes of content based on the preferences of a user is described. A segmentation platform causes, at least in part, a segmentation of content into one or more segments, wherein the one or more segments are associated with one or more content labels. The segmentation platform also causes, at least in part, a rendering and/or sharing of one or more remixes of the content based, at least in part, on at least one subset of the one or more segments based, at least in part, on profile information, context information, or a combination thereof associated with one or more viewers of the content, one or more owners of the content, one or more sharers of the content.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: August 19, 2014
    Assignee: Nokia Corporation
    Inventors: Sailesh Kumar Sathish, Sujeet Shyamsundar Mate
  • Publication number: 20140211622
    Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: NETSPEED SYSTEMS
    Inventors: Sailesh Kumar, Eric Norige, Joji Philip, Mahmud Hassan, Sundari Mitra, Joseph Rowlands
  • Publication number: 20140204735
    Abstract: Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: Netspeed Systems
    Inventors: Sailesh KUMAR, Eric NORIGE, Joji PHILIP, Mahmud HASSAN, Sundari MITRA, Joseph ROWLANDS
  • Publication number: 20140204764
    Abstract: Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: Netspeed Systems
    Inventors: Sailesh KUMAR, Eric NORIGE, Joji PHILIP, Mahmud HASSAN, Sundari MITRA, Joseph ROWLANDS
  • Patent number: 8787379
    Abstract: An apparatus comprising a plurality of nodes and a plurality of links connecting the nodes in a ring topology, wherein a first node from among the plurality of nodes is coupled to a first link from among the plurality of links, wherein the first link comprises a plurality of virtual channels, and wherein each of the plurality of virtual channels is assigned to provide service to a unique one of the plurality of nodes.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: July 22, 2014
    Assignee: Futurewei Technologies, Inc.
    Inventors: Rohit Sunkam Ramanujam, Sailesh Kumar, William Lynch
  • Publication number: 20140177648
    Abstract: Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve tagging the messages with meta-information when the messages are injected in the interconnection network. Example implementations may involve routers using various arbitration phases, and making local arbitration decisions based on the meta-information of incoming messages. The meta-information can be of various types based on the number of router arbitration phases, and the desired level of sophistication.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: NetSpeed Systems
    Inventors: Sailesh KUMAR, Eric NORIGE, Joji PHILIP, Mahmud HASSAN, Sundari MITRA, Joseph ROWLANDS
  • Publication number: 20140177473
    Abstract: A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: NetSpeed Systems
    Inventors: Sailesh KUMAR, Eric NORIGE, Joji PHILIP, Mahmud HASSAN, Sundari MITRA, Joseph ROWLANDS
  • Patent number: 8756002
    Abstract: An approach is provided for providing aggregated position-related information at a user interface based on invocation conditions. An invocation platform determines one or more applications, one or more services, or a combination thereof that provide position-related information. The invocation platform further determines one or more invocation conditions associated with the position-related information, the one or more applications, the one or more services, or a combination thereof. The invocation platform also causes, at least in part, a presentation of at least one user interface that aggregates the position-related information from the one or more applications, the one or more services, or a combination thereof based, at least in part, on the one or more invocation conditions.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: June 17, 2014
    Assignee: Nokia Corporation
    Inventor: Sailesh Kumar Sathish