Abstract: A method for treating an effluent gas from a semiconductor processing system includes the steps of exhausting the effluent gas from a processing chamber, and catalytically treating the effluent gas with the at least one mixed metal oxide. The effluent gas includes unconsumed process gasses introduced during semiconductor processing operations, such as during chemical vapor deposition (CVD) and plasma-reactive ion etching. The mixed metal oxide may include a hetero bi-metal oxide, a hetero tri-metal oxide, or a perovskite. A hetero bi-metal oxide includes LaCoO3 and LaMnO3, for example, and a hetero tri-metal oxide includes (LaxPr1−x)CoO3 and (LaxPr1−x)MnO3, for example. The effluent gas may include at least carbon monoxide and/or ozone. Thus, catalytically treating the effluent gas preferably includes the catalytically converting carbon monoxide to carbon dioxide and/or ozone to oxygen.

Abstract: A polishing fluid comprising a distributed organic phase and a continuous aqueous phase. The distributed phase has at least one complexing agent and the aqueous phase has abrasive particles dispersed therein. Reaction products generated during polishing interact with the complexing agent(s) to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.

Abstract: A CMP slurry includes a first emulsion having a continuous aqueous phase and a second emulsion. The first emulsion includes abrasive particles, and the second emulsion captures metal particles polished from the semiconductor wafer. Thus, metal particles can be removed from the slurry during CMP to avoid damaging and/or contaminating the semiconductor wafer.

Abstract: The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.

Abstract: An integrated circuit includes a substrate, and at least one copper interconnection layer adjacent the substrate. The interconnection layer further comprises copper lines, each comprising at least an upper surface portion including at least one copper fluoride compound. The copper fluoride compound preferably comprises at least one of cuprous fluoride and cupric fluoride. The compounds of copper and fluoride are relatively stable and provide a reliable and long term passivation for the underlying copper. In accordance with one particularly advantageous embodiment of the invention, the dielectric layer may comprise a fluorosilicate glass (FSG) layer. Accordingly, during formation of the FSG layer, the upper surface of the copper reacts with the fluorine to form the copper fluoride compound which then acts as the passivation layer for the underlying copper. In other embodiments, the dielectric layer may comprise an oxide or air, for example.

Abstract: A method and structure is described which substantially eliminates the grain growth of copper due to self annealing. Basically, by alloying the copper interconnect e.g. with Cr, Co, Zn or Ag in an amount which does not cause a second phase or precipitation at the annealing temperature, one can control and maintain the grain size of the copper and hence achieve a uniform microstructure while improving the strength, hardness and CMP removal rate of the interconnect while substantially maintaining the conductivity of the copper.

Abstract: A chemical mechanical polishing (CMP) system includes a polishing device including a polishing article. The polishing device holds the semiconductor wafer and provides relative movement between the semiconductor wafer and the polishing article with a slurry therebetween. The CMP system also includes a slurry processor for processing used slurry from the polishing device and for delivering processed slurry to the polishing device. The slurry processor including a metal separator for separating metal particles, polished from the semiconductor wafer, from the used slurry. The slurry can be continuously recirculated during a CMP process without damaging and/or contaminating the layers of the semiconductor wafer.

Abstract: A method of fabricating a metal-oxide-metal capacitor in a microelectronic device is provided. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is further deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor.

Abstract: A titanium nitride barrier within an integrated contact structure is formed as multi-layered stack. The multi-layering of the titanium nitride thus provides improved junction integrity since the multi-layer structure exhibits improved mechanical stability when compared to conventional single layer arrangements. The multi-layer titanium nitride barrier may be used as either a conventional interconnect metallization or as a nucleation structure within a tungsten plug. The multi-layer structure may be formed to include an overall thickness less than a conventional single layer, yet provide for improved stress accommodation, resulting in eliminating micro-cracks within the titanium nitride (and as a result eliminating the un-wanted diffusion of aluminum or tungsten precursors through the titanium nitride).

Abstract: Interconnects in porous dielectric materials are coated with a SiC-containing material to inhibit moisture penetration and retention within the dielectric material. Specifically, SiC coatings doped with boron such as SiC(BN) show particularly good results as barrier layers for dielectric interconnects.

Abstract: An integrated circuit capacitor includes a metal plug in a dielectric layer adjacent a substrate. The metal plug has at least one topographical defect in an uppermost surface portion thereof. A lower metal electrode overlies the dielectric layer and the metal plug. The lower metal electrode includes, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer overlies the lower metal electrode, and an upper metal electrode overlies the capacitor dielectric layer. An advantage of this structure is that the stack of metal layers of the lower metal electrode, will prevent undesired defects at the surface of the metal plug from adversely effecting device reliability or manufacturing yield.

Abstract: An unwanted tungsten film deposit on a Chemical Vapor Deposition chamber is cleaned by adding a mixture of at least two cleaning gases into the chamber at a predetermined temperature and pressure and in contact with said chamber walls for a sufficient length of time. The cleaning gases and reacted tungsten species are removed from the chamber by vacuum, and unreacted cleaning gases are removed by purging the chamber with an inert gas. At least one cleaning gas is selected from the group consisting of bromomethane, dibromomethane, bromoform and mixtures thereof. The temperature of the chamber is preferably at least about 300 degrees Celsius. The cleaning gases in the chamber are at a pressure in the range from about 100 to 200 Torr and the chamber is purged at a pressure in the range from about 200 to 500 Torr.

Abstract: A polishing fluid comprising a distributed organic phase and a continuous aqueous phase. The distributed phase has at least one complexing agent and the aqueous phase has abrasive particles dispersed therein. Reaction products generated during polishing interact with the complexing agent(s) to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.

Abstract: A method of fabricating a metal-oxide-metal capacitor in a microelectronic device is provided. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is further deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor.

Abstract: A polishing pad formed from closed-cell elastomer foam includes a population of bubbles within the pad. As the pad wears due to polishing and the polishing surface recedes, the freshly formed polishing surface includes pores formed of the newly exposed bubbles. The pores receive and retain polishing slurry and aid in the chemical mechanical polishing process. Pad conditioning is not required because new pores are constantly being created at the pad surface as the surface recedes during polishing. The method for forming the polishing pad includes the injection of gas bubbles into the viscous elastomer material used to form the pad. Process conditions are chosen to maintain gas bubbles within the elastomer material during the curing and solidifying process steps.

Abstract: A process for forming a dual damascene structure. The process includes forming a stack including insulating layers and a stop layer where two masks are formed above the stack. One of the masks is used to form via or contact openings in the insulating layers and the second mask is used to form grooves for interconnections in the insulating layers.

Abstract: A chemical mechanical polishing (CMP) system includes a polishing device including a polishing article. The polishing device provides relative movement between the semiconductor wafer and the polishing article with a slurry therebetween. The slurry preferably includes abrasive particles and a photocatalyst to enhance oxidation of metal of the semiconductor wafer. The slurry may also include water and the photocatalyst is a mixed metal oxide for breaking down water into hydrogen and oxygen in the presence of light.

Abstract: The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a plug, planarizing the substrate, patterning the substrate to expose the first material, forming an electrode material layer over the substrate, and patterning the electrode material layer, whereby the first material is substantially encapsulated by the electrode material layer.

Abstract: A method an apparatus for making copper metallic interconnects for semiconductors having an oxide layer deposited in the copper in situ during the deposition of the copper within the via.

Abstract: A new capacitor and a new method for fabricating the capacitor in an integrated circuit. The method uses fewer steps than those used in prior art processes. In accordance with the invention, trenches of differing depths are formed in a first insulating layer. One of the trenches is etched to expose a conducting layer formed under the insulating layer. Conductive material is deposited in the trenches to form a capacitor. The trenches are formed apart from each other.