Abstract: A CMOS gate structure comprises a multilayered polysilicon structure and a deposited silicide layer, with a nitridized silicide barrier layer formed therebetween. The multilayered polysilicon will exhibit a relatively large grain size and uniform structure. The deposited silicide layer is annealed to mimic the polysilicon grain size and structure. The combination of the tailored grain structure with the intermediate barrier layer results in a gate structure that is essentially impervious to subsequent dopant diffusions.

Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an antireflective coating to prevent rainbowing or spiking of the coating into the underlying metal.

Abstract: A method of making a semiconductor device includes forming at least one opening, having vertical sidewalls and a bottom, in a first dielectric layer adjacent a substrate. A second dielectric layer is formed to line the vertical sidewalls of the at least one opening, and has a relatively lower etch rate than the first dielectric layer. A conductive layer is deposited to fill the at least one opening and an upper surface of the semiconductor wafer is cleaned. The method preferably includes the steps of depositing a barrier layer lining the second dielectric layer and the bottom of the at least one opening, and chemically mechanically polishing the semiconductor wafer with the second dielectric layer protecting upper edges of the barrier layer and conductive layer.

Abstract: The invention is a method and resulting device which provides a strong bond between a silicon substrate and an oxide component mounted within a cavity in the substrate. A layer of titanium, for example, is deposited on the walls of the cavity, followed by deposition of a layer of aluminum. The structure is preferably annealed to form titanium silicide and titanium-aluminum interface layers. The component is then bonded to the aluminum layer.

Abstract: The specification describes a process for making gate electrodes for silicon MOS transistor devices. The gate electrode is a composite of a first layer of tungsten suicide, a second layer of tungsten silicide nitride, and a third layer of tungsten silicide. The absence of polysilicon as a main constituent of the gate electrode eliminates depletion effects. The presence of nitride in the composite gate electrode impedes updiffusion of boron from the source and drain. The layers are preferably formed in situ in an PVD apparatus.

Abstract: A method for making an integrated circuit capacitor includes forming a first dielectric layer adjacent a substrate, forming a first opening in the first dielectric layer, filling the first opening with a conductive material to define a first metal plug, and forming a trench in the first dielectric layer adjacent the first metal plug. An interconnection line lines the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. The method further includes forming a second dielectric layer on the interconnection line, forming a second opening in the second dielectric layer, and filling the second opening with a conductive metal to define a second metal plug having a body portion and anchor portions extending downward from the body portion for engaging the anchoring recesses to anchor the second metal plug. A second trench is formed in the second dielectric layer adjacent the second metal plug, and is aligned with the first trench.

Abstract: Interconnects in porous dielectric materials are coated with a SiC-containing material to inhibit moisture penetration and retention within the dielectric material. Specifically, SiC coatings doped with boron such as SiC(BN) show particularly good results as barrier layers for dielectric interconnects.

Abstract: The invention is a method and resulting device which provides a strong bond between a silicon substrate and an oxide component mounted within a cavity in the substrate. A layer of titanium, for example, is deposited on the walls of the cavity, followed by deposition of a layer of aluminum. The structure is preferably annealed to form titanium silicide and titanium-aluminum interface layers. The component is then bonded to the aluminum layer.

Abstract: A semiconductor device process for forming a multilayered nitride structure. The nitride is used as either isolation or as part of a dielectric structure. The deposition rate for the nitride is varied to form a multilayered structure with stress accommodation at the interface between sub-layers in the multilayer structure. In addition, the sub-layered structure reduces pin-holes and microcracks in the nitride film and improves the overall uniformity in thickness of the final nitride film.

Abstract: The specification describes a composite TiN barrier layer structure formed by depositing a first TiN layer by CVD to obtain good step coverage, followed by a second TiN layer formed by PVD to obtain uniform surface morphology for subsequent deposition of an aluminum alloy contact layer. Alternatively, uniform TiN layer morphology is obtained by depositing multiple CVD TiN layers as a series of thin strata, and passivating after each deposition step to fully crystallize each stratum thereby obtaining a uniformly crystallized barrier layer.

Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an anti-reflective coating to prevent rainbowing or spiking of the coating into the underlying metal.

Abstract: The present invention provides methods of calibrating a deposition device, which is preferably a vapor deposition device, and more preferably is a physical vapor deposition device. One of the methods includes the steps of: (1) determining a resistance-temperature relationship of a substance located on a semiconductor wafer, a resistance of the substance being a function of a temperature of said semiconductor wafer; (2) placing the semiconductor wafer in the deposition device; (3) heating the heater to a known temperature; and (4) measuring a resistance of the substance, the resistance-temperature relationship allowing a relationship between a temperature of the semiconductor wafer and the known temperature to be determined, thereby to allow the deposition device to be calibrated.

Abstract: Undesirable counter doping of n.sup.+ /p.sup.+ gates illustratively through cross diffusion through an overlying silicide is inhibited by insertion of layers of titanium nitride and titanium, tungsten or tantalum between the polysilicon gates and an overlying silicide.

Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an anti-reflective coating to prevent rainbowing or spiking of the coating into the underlying metal.

Abstract: A method of forming electromigration resistant integrated circuit runners is disclosed. A collimated beam of particles is directed toward a substrate to form a metal nucleating layer. Then a non-collimated beam is used to form the rest of the metal layer. Then the layers are patterned to form runners.

Abstract: Integrated circuit fabrication includes the formation of tungsten contacts in windows. Between the tungsten and the contact region are Ti and TiN layers. Defects are prevented or reduced by sealing grain boundaries in the TiN layer prior to tungsten deposition. Grain boundaries are sealed by rinsing the TiN layer in water at ambient temperature or above.

Abstract: A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems.