Patents by Inventor Sampath K. Ratnam

Sampath K. Ratnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Temperature related error management
    Patent number: 10579468
    Abstract: Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an array of memory cells and a write temperature indicator appended to at least one predetermined number of bytes of the stored data in the array of memory cells. The apparatuses can include a controller configured to determine a numerical temperature difference between the write temperature indicator and a read temperature indicator and determine, from stored operations, an error management operation for the stored data based, at least in part, on comparison of the numerical temperature difference to a temperature difference threshold.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam
  • Memory having a static cache and a dynamic cache
    Patent number: 10579537
    Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher S. Hale, Sampath K. Ratnam, Kishore K. Muchherla
  • Read disturb scan consolidation
    Patent number: 10553290
    Abstract: A processing device in a memory system determines that a first read count of a first data block on a first plane of a memory component satisfies a first threshold criterion. The processing device further determines whether a second read count of a second data block on a second plane of the memory component satisfies a second threshold criterion, wherein the second block is associated with the first block, and wherein the second threshold criterion is lower than the first threshold criterion. Responsive to the second read count satisfying the second threshold criterion, the processing device performs a multi-plane scan to determine a first error rate for the first data block and a second error rate for the second data block in parallel.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish R. Singidi, Shane Nowell, Vamsi Pavan Rayaprolu, Sampath K. Ratnam
  • EXTENDED CROSS-TEMPERATURE HANDLING IN A MEMORY SUB-SYSTEM
    Publication number: 20200026462
    Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
    Type: Application
    Filed: July 20, 2018
    Publication date: January 23, 2020
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
  • Providing data of a memory system based on an adjustable error rate
    Patent number: 10540228
    Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: January 21, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Mustafa N. Kaynak, Larry J. Koudele, Michael Sheperek, Patrick R Khayat, Sampath K Ratnam
  • Setting a default read signal based on error correction
    Patent number: 10535419
    Abstract: The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. Methods can include reading a page of data from the group of memory cells with a second discrete read signal different than the first discrete read signal and error correcting at least one codeword of the page of data as read with the second discrete read signal. One of the first and the second discrete read signals can be set as a default read signal based at least in part on the respective error corrections.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sampath K. Ratnam, Satish K. Yanamanamanda
  • Memory device with dynamic cache management
    Patent number: 10509722
    Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
  • IDENTIFYING ASYNCHRONOUS POWER LOSS
    Publication number: 20190370099
    Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga, Sampath K. Ratnam, Walter Di-Francesco, Renato C. Padilla, JR., Yun Li, Kishore Kumar Muchherla
  • ADAPTIVE SCAN FREQUENCY FOR DETECTING ERRORS IN A MEMORY SYSTEM
    Publication number: 20190354421
    Abstract: Performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device, determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing, and performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: Kevin R. Brandt, William C. Filipiak, Michael G. McNeeley, Kishore K. Muchherla, Sampath K. Ratnam, Akira Goda, Todd A. Marquart
  • PERFORMING AN OPERATION ON A MEMORY CELL OF A MEMORY SYSTEM AT A FREQUENCY BASED ON TEMPERATURE
    Publication number: 20190341117
    Abstract: A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Peter Feeley, Kishore Kumar Muchherla, Renato C. Padilla, Shane Nowell
  • Memory management
    Patent number: 10452282
    Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Preston A. Thomson, Renato C. Padilla, Ashutosh Malshe
  • Identifying asynchronous power loss
    Patent number: 10430262
    Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga, Sampath K. Ratnam, Walter Di-Francesco, Renato C. Padilla, Jr., Yun Li, Kishore Kumar Muchherla
  • Threshold voltage margin analysis
    Patent number: 10418122
    Abstract: The present disclosure is related to a threshold voltage margin analysis. An example embodiment apparatus can include a memory and a controller coupled to the memory. The controller is configured to determine a previous power loss of a memory to be an asynchronous power loss, and identify a portion of the memory last subject to programming operations during the determined asynchronous power loss. The controller is further configured to perform a threshold voltage (Vt) margin analysis on the portion of the memory responsive to the determined asynchronous power loss.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Abolfazl Rashwand
  • STORING PAGE WRITE ATTRIBUTES
    Publication number: 20190278491
    Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.
    Type: Application
    Filed: March 6, 2018
    Publication date: September 12, 2019
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
  • ADJUSTING A PARAMETER FOR A PROGRAMMING OPERATION BASED ON THE TEMPERATURE OF A MEMORY SYSTEM
    Publication number: 20190278510
    Abstract: A temperature related to a memory device is identified. It is determined whether the temperature related to the memory device satisfies a threshold temperature condition. Responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, a parameter for a programming operation is adjusted from a first value to a second value to store data at the memory device.
    Type: Application
    Filed: March 6, 2018
    Publication date: September 12, 2019
    Inventors: Mustafa N. Kaynak, Sampath K. Ratnam, Zixiang Loh, Nagendra Prasad Ganesh Rao, Larry J. Koudele, Vamsi Pavan Rayaprolu, Patrick R. Khayat, Shane Nowell
  • PROVIDING DATA OF A MEMORY SYSTEM BASED ON AN ADJUSTABLE ERROR RATE
    Publication number: 20190278655
    Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 12, 2019
    Inventors: Larry J. KOUDELE, Mustafa N. KAYNAK, Michael SHEPEREK, Patrick R. KHAYAT, Sampath K. RATNAM
  • MEMORY MANAGEMENT
    Publication number: 20190278490
    Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • GARBAGE COLLECTION
    Publication number: 20190272098
    Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 5, 2019
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla, Ashutosh Malshe, Harish R. Singidi
  • METHODS OF ERROR-BASED READ DISTURB MITIGATION AND MEMORY DEVICES UTILIZING THE SAME
    Publication number: 20190272881
    Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
    Type: Application
    Filed: May 18, 2019
    Publication date: September 5, 2019
    Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
  • Performing an operation on a memory cell of a memory system at a frequency based on temperature
    Patent number: 10403378
    Abstract: A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: September 3, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Peter Feeley, Kishore Kumar Muchherla, Renato C. Padilla, Shane Nowell