Patents by Inventor Sampath K. Ratnam

Sampath K. Ratnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MANAGEMENT OF PROGRAM SUSPEND AND RESUME OPERATIONS OF A MEMORY SUB-SYSTEM
    Publication number: 20200285416
    Abstract: A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Inventors: Jiangang Wu, Sampath K. Ratnam, Yang Zhang, Guang Chang Ye, Kishore Kumar Muchherla, Hong Lu, Karl D. Schuh, Vamsi Pavan Rayaprolu
  • Memory devices and methods for read disturb mitigation involving word line scans to detect localized read disturb effects and to determine error count in tracked sub sets of memory addresses
    Patent number: 10770156
    Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
    Type: Grant
    Filed: May 18, 2019
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
  • Scan frequency modulation based on memory density or block usage
    Patent number: 10761727
    Abstract: A region of a memory component is determined to include a type of memory. A frequency to perform an operation on the region of the memory component is determined based on the type of memory. The operation is performed on a memory cell at the region of the memory component at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 1, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Ashutosh Malshe, Kishore Kumar Muchherla
  • Adjusting a parameter for a programming operation based on the temperature of a memory system
    Patent number: 10732890
    Abstract: A temperature related to a memory device is identified. It is determined whether the temperature related to the memory device satisfies a threshold temperature condition. Responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, a parameter for a programming operation is adjusted from a first value to a second value to store data at the memory device.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 4, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Mustafa N. Kaynak, Sampath K. Ratnam, Zixiang Loh, Nagendra Prasad Ganesh Rao, Larry J. Koudele, Vamsi Pavan Rayaprolu, Patrick R. Khayat, Shane Nowell
  • READ WINDOW SIZE
    Publication number: 20200210259
    Abstract: A processing device in a memory system receives a memory command indicating a read window size and a first read voltage and identifies a read window for a first data block of the memory component having the read window size and centered at the first read voltage. The processing device determines whether a number of bit flips for the first data block within the read window exceeds an error threshold and, in response to the number of bit flips exceeding the error threshold, refreshes data stored on the first data block of the memory component.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 2, 2020
    Inventors: Jung Sheng Hoei, Peter Sean Feeley, Sampath K. Ratnam, Sead Zildzic, Kishore Kumar Muchherla
  • GARBAGE COLLECTION CANDIDATE SELECTION USING BLOCK OVERWRITE RATE
    Publication number: 20200210330
    Abstract: A processing device in a memory system determines whether a first data block of a plurality of data blocks on the memory component satisfies a first threshold criterion pertaining to a first number of the plurality of data blocks having a lower amount of valid data than a remainder of the plurality of data blocks. Responsive to the first data block satisfying the first threshold criterion, the processing device determines whether the first data block satisfies a second threshold criterion pertaining to a second number of the plurality of data blocks having been written to more recently than the remainder of the plurality of data blocks. Responsive to the first data block satisfying the second threshold criterion, the processing device determines whether a rate of change of an amount of valid data on the first data block satisfies a third threshold criterion.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 2, 2020
    Inventors: Kishore Kumar MUCHHERLA, Sampath K. RATNAM, Ashutosh MALSHE, Peter Sean FEELEY
  • USING A COMMON POOL OF BLOCKS FOR USER DATA AND A SYSTEM DATA STRUCTURE
    Publication number: 20200210331
    Abstract: A request to add content to a system data structure can be received. A first set of blocks of a common pool of blocks are allocated to the system data structure and a second set of blocks of the common pool of blocks are allocated to user data. A determination can be made as to whether a garbage collection operation associated with the first set of blocks of the common pool allocated to the system data structure satisfies a garbage collection performance condition. Responsive to determining that the garbage collection operation satisfies the garbage collection performance condition, a block from the common pool can be allocated to the first set of blocks allocated to the system data structure.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Kishore Kumar Muchherla, Kulachet Tanpairoj, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • MITIGATING AN UNDETECTABLE ERROR WHEN RETRIEVING CRITICAL DATA DURING ERROR HANDLING
    Publication number: 20200201710
    Abstract: A processing device reads data from a memory device in response to a received request and performs a first error control operation on the data based on an initial operating characteristic to correct one or more errors in the data. The processing device determines that the first error control operation based on the initial operating characteristic failed to correct the one or more errors in the data, modifies the initial operating characteristic to generate a modified operating characteristic and performs a second error control operation on the data based on the modified operating characteristic to correct the one or more errors in the data.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 25, 2020
    Inventors: Vamsi Pavan Rayaprolu, Sivagnanam Parthasarathy, Sampath K. Ratnam, Shane Nowell, Renato C. Padilla
  • Performing an operation on a memory cell of a memory system at a frequency based on temperature
    Patent number: 10685725
    Abstract: A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 16, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Peter Feeley, Kishore Kumar Muchherla, Renato C. Padilla, Shane Nowell
  • MEMORY HAVING A STATIC CACHE AND A DYNAMIC CACHE
    Publication number: 20200183852
    Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Christopher S. Hale, Sampath K. Ratnam, Kishore K. Muchherla
  • Storing page write attributes
    Patent number: 10671298
    Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
  • SCAN FREQUENCY MODULATION BASED ON MEMORY DENSITY OR BLOCK USAGE
    Publication number: 20200159410
    Abstract: A region of a memory component is determined to include a type of memory. A frequency to perform an operation on the region of the memory component is determined based on the type of memory. The operation is performed on a memory cell at the region of the memory component at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Ashutosh Malshe, Kishore Kumar Muchherla
  • PROVIDING DATA OF A MEMORY SYSTEM BASED ON AN ADJUSTABLE ERROR RATE
    Publication number: 20200151058
    Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Mustafa N. Kaynak, Larry J. Koudele, Michael Sheperek, Patrick R. Khayat, Sampath K. Ratnam
  • READ DISTURB SCAN CONSOLIDATION
    Publication number: 20200152280
    Abstract: A processing device in a memory system determines that a first metric of a first memory unit on a first plane of a memory device satisfies a first threshold criterion. The processing device further determines whether a second metric of a second memory unit on a second plane of the memory device satisfies a second threshold criterion, wherein the second block is associated with the first block, and wherein the second threshold criterion is lower than the first threshold criterion. Responsive to the second metric satisfying the second threshold criterion, the processing device performs a multi-plane data integrity operation to determine a first reliability statistic for the first memory unit and a second reliability statistic for the second memory unit in parallel.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish R. Singidi, Shane Nowell, Vamsi Pavan Rayaprolu, Sampath K. Ratnam
  • RELOCATING DATA TO LOW LATENCY MEMORY
    Publication number: 20200133585
    Abstract: A first data block of multiple data blocks is identified in a first portion of the memory component, the first data block being identified based on a read count associated with the first data block satisfies a first threshold criterion. A determination is made as to whether a second portion of the memory component has an amount of unused storage to store data stored at the first data block, wherein the second portion of the memory component is associated with a lower read latency than the first portion. In response to determining that the second portion of the memory component has the amount of unused storage to store the data stored at the first data block, data stored at the first data block in the first portion of the memory component is relocated to a second data block in the second portion of the memory component. An error rate is evaluated on each word line in the first data block.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Peter Feeley
  • PERIODIC FLUSH IN MEMORY COMPONENT THAT IS USING GREEDY GARBAGE COLLECTION
    Publication number: 20200133843
    Abstract: An amount of valid data for each data block of multiple data blocks stored at a first memory is determined. An operation to write valid data of a particular data block from the first memory to a second memory is performed based on the amount of valid data for each data block. A determination is made that a threshold condition associated with when valid data of the data blocks was written to the first memory has been satisfied. In response to determining that the threshold condition has been satisfied, the operation to write valid data of the data blocks from the first memory to the second memory is performed based on when the valid data was written to the first memory.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale
  • POWER-ON-TIME BASED DATA RELOCATION
    Publication number: 20200133834
    Abstract: A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Kishore Kumar MUCHHERLA, Renato C. PADILLA, Sampath K. RATNAM, Saeed SHARIFI TEHRANI, Peter FEELEY, Kevin R. BRANDT
  • Mitigating an undetectable error when retrieving critical data during error handling
    Patent number: 10606698
    Abstract: A determination can be made that an error control operation associated with user data has failed. An initial operating characteristic associated with the error control operation that failed can be identified. A complementary operating characteristic to replace the operating characteristic associated with the error control operation that failed can be determined. The error control operation for the user data can be performed based on the complementary operating characteristic.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 31, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Vamsi Pavan Rayaprolu, Sivagnanam Parthasarathy, Sampath K. Ratnam, Shane Nowell, Renato C. Padilla
  • MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT
    Publication number: 20200097402
    Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, and designate a storage mode for an available memory block based on the valid data, wherein the storage mode is for configuring memory cells in the available memory block as cache memory that stores a number of bits less than maximum storage capacities thereof for subsequent or upcoming data writes.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
  • TEMPERATURE COMPENSATION IN A MEMORY SYSTEM
    Publication number: 20200073451
    Abstract: A processing device in a memory system receives a data access request identifying a memory cell in a first segment of the memory system comprising at least a portion of at least one memory device. The processing device determines a temperature difference between a current temperature associated with the memory cell and a baseline temperature of the memory system and identifies a temperature compensation value specific to the first segment of the memory system, the temperature compensation value corresponding to the temperature difference. The processing device adjusts, based on an amount represented by the temperature compensation value, an access control voltage applied to the memory cell.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Shane Nowell, Sampath K. Ratnam, Vamsi Pavan Rayaprolu