Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.

Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.

Abstract: Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.

Abstract: A processing device of a memory sub-system is configured to identify a plurality of blocks assigned to a first voltage bin of a plurality of voltage bins of a memory device; identify a subset of the plurality of blocks having a time after program (TAP) within a predetermined threshold period of time from a second TAP associated with a transition boundary between the first voltage bin and a subsequent voltage bin of the plurality of voltage bins; determine a threshold voltage offset associated with the subset of blocks; and associate the threshold voltage offset with the subsequent voltage bin.

Abstract: A processing device in a memory sub-system stores data at a first voltage level in a memory cell in a first segment of the memory sub-system, and determines a temperature change between a current temperature associated with the memory cell and a new temperature. The processing device further determines a voltage level read from the memory cell at the new temperature, determines a difference between the voltage level read from the memory cell and the first voltage level, and determines a temperature compensation value based on the difference between the voltage level read from the memory cell and the first voltage level in view of the temperature change.

Abstract: A processing device in a memory system assigns a memory page to a sensitivity tier of a plurality of sensitivity tiers. The processing device determines respective scan intervals for the plurality of sensitivity tiers, wherein the respective scan intervals are based on at least one characteristic of a memory device, the at least one characteristic comprising memory cell margins of the memory device. The processing device scans a subset of a plurality of memory pages, wherein the subset comprises a number of memory pages from each sensitivity tier identified according to the respective scan intervals.

Abstract: A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level of a pass voltage that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied during a program operation to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can exceed the pass voltage applied to the unselected wordlines of the memory component during the read operation.

Abstract: A method includes identifying, by a processing device, a common pool of blocks comprising a first plurality of blocks allocated to system data and a second plurality of blocks allocated to user data; determining whether user data has been written to the second plurality of blocks within a threshold period of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold period of time, allocating a block from the second plurality of blocks to the first plurality of blocks.

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment of the plurality of block segments; scan a second block at a second boundary of the first block segment; identify, based on a scanning result of the first block, a first voltage bin associated with the first block; identify, based on a second scanning result of the second block, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block of a subset of the plurality of blocks assigned to the first block segment.

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.

Abstract: A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped.

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

Abstract: A first host data item and a second host data item are received. The first host data item is stored in a first page of a first logical unit of a memory device, where the first page is one of a plurality of pages associated with redundancy metadata. A second page a second page of a second logical unit of the memory device is identified, where the second page is one of the plurality of pages associated with the redundancy metadata, and the first page and the second page are associated with different wordlines of the memory device. The second host data item is stored in the second page of the second logical unit of the memory device. The first page and the second page can be associated with a fault tolerant stripe that includes the redundancy metadata.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.

Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.