Patents by Inventor Sampath K. Ratnam

Sampath K. Ratnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELECTIVE ACCELERATED SAMPLING OF FAILURE-SENSITIVE MEMORY PAGES
    Publication number: 20220229564
    Abstract: A processing device in a memory system assigns a memory page to a sensitivity tier of a plurality of sensitivity tiers. The processing device determines respective scan intervals for the plurality of sensitivity tiers, wherein the respective scan intervals are based on at least one characteristic of a memory device, the at least one characteristic comprising memory cell margins of the memory device. The processing device scans a subset of a plurality of memory pages, wherein the subset comprises a number of memory pages from each sensitivity tier identified according to the respective scan intervals.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Inventors: Kishore Kumar Muchherla, Gary F. Besinga, Cory M. Steinmetz, Pushpa Seetamraju, Jiangang Wu, Sampath K. Ratnam, Peter Feeley
  • GROUPING BLOCKS BASED ON POWER CYCLE AND POWER ON TIME
    Publication number: 20220229554
    Abstract: A block family associated with a memory device is initialized. An initial value of a power cycle count associated with the memory device is stored. Responsive to programming a block residing in the memory device, the block is associated with the block family. Responsive to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, the block family is closed. Responsive to determining that a time period that has elapsed since initializing the block family exceeds a threshold period, the block family is closed.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 21, 2022
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley, Karl D. Schuh
  • Mitigating a voltage condition of a memory cell in a memory sub-system
    Patent number: 11393541
    Abstract: A determination that a programming operation has been performed on a memory cell can be made. An amount of time that has elapsed since the programming operation has been performed on the memory cell can be identified. A determination as to whether the amount of time that has elapsed satisfies a threshold time condition can be made. In response to determining that the amount of time that has elapsed satisfies the threshold time condition an operation can be performed on the memory cell to change or maintain a voltage condition of the memory cell.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
  • Workload adaptive scans for memory sub-systems
    Patent number: 11393548
    Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Renato C. Padilla, Sampath K. Ratnam, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Gary F. Besinga, Michael G. Miller, Tawalin Opastrakoon
  • Power-on-time based data relocation
    Patent number: 11379355
    Abstract: A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Renato C. Padilla, Sampath K. Ratnam, Saeed Sharifi Tehrani, Peter Feeley, Kevin R. Brandt
  • WORKLOAD ADAPTIVE SCANS FOR MEMORY SUB-SYSTEMS
    Publication number: 20220199179
    Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Inventors: Renato C. Padilla, Sampath K. Ratnam, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Gary F. Besinga, Michael G. Miller, Tawalin Opastrakoon
  • DYNAMIC PROGRAM-VERIFY VOLTAGE ADJUSTMENT FOR INTRA-BLOCK STORAGE CHARGE LOSS UNIFORMITY
    Publication number: 20220188226
    Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 16, 2022
    Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe
  • Scan frequency modulation based on memory density or block usage
    Patent number: 11354037
    Abstract: A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Ashutosh Malshe, Kishore Kumar Muchherla
  • CACHE MANAGEMENT BASED ON MEMORY DEVICE OVER-PROVISIONING
    Publication number: 20220156187
    Abstract: System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid management units in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid management units on the memory device based on the amount of valid management units. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid management units.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 19, 2022
    Inventors: Kevin R. Brandt, Peter Feeley, Kishore Kumar Muchherla, Yun Li, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale, Daniel J. Hubbard
  • EXTENDED CROSS-TEMPERATURE HANDLING IN A MEMORY SUB-SYSTEM
    Publication number: 20220129204
    Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
    Type: Application
    Filed: November 1, 2021
    Publication date: April 28, 2022
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
  • Selective accelerated sampling of failure-sensitive memory pages
    Patent number: 11301143
    Abstract: A processing device in a memory system determines sensitivity value of a memory page in the memory system. The processing device assigns the memory page to a sensitivity tier of a plurality of sensitivity tiers based on a corresponding sensitivity value, wherein each sensitivity tier has a corresponding range of sensitivity values. The processing device further determines a targeted scan interval for each sensitivity tier of the plurality of sensitivity tiers and scans a subset of a plurality of memory pages in the memory component, wherein the subset comprises a number of memory pages from each sensitivity tier determined according to the corresponding targeted scan interval of each sensitivity tier.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Gary F. Besinga, Cory M. Steinmetz, Pushpa Seetamraju, Jiangang Wu, Sampath K. Ratnam, Peter Feeley
  • Storing page write attributes
    Patent number: 11301146
    Abstract: A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
  • MEMORY DEVICES AND ELECTRONIC SYSTEMS HAVING A HYBRID CACHE INCLUDING STATIC AND DYNAMIC CACHES, AND RELATED METHODS
    Publication number: 20220091740
    Abstract: Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Sampath k. Ratnam, Peter Feeley, Michael G. Miller, Christopher S. Hale, Renato C. Padilla
  • PROVIDING DATA OF A MEMORY SYSTEM BASED ON AN ADJUSTABLE ERROR RATE
    Publication number: 20220091935
    Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 24, 2022
    Inventors: Mustafa N. Kaynak, Larry J. Koudele, Michael Sheperek, Patrick R. Khayat, Sampath K. Ratnam
  • MANAGING BLOCK RETIREMENT FOR TEMPORARY OPERATIONAL CONDITIONS
    Publication number: 20220068422
    Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.
    Type: Application
    Filed: November 8, 2021
    Publication date: March 3, 2022
    Inventors: Kishore Kumar Muchherla, Sampath K. Ratnam, Scott A. Stoller, Preston A. Thomson, Kevin R. Brandt, Marc S. Hamilton, Christopher S. Hale
  • Cache management based on memory device over-provisioning
    Patent number: 11256620
    Abstract: System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid blocks in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid blocks on the memory device based on the amount of valid blocks. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid blocks.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Brandt, Peter Feeley, Kishore Kumar Muchherla, Yun Li, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale, Daniel J. Hubbard
  • DATA BLOCK SWITCHING AT A MEMORY SUB-SYSTEM
    Publication number: 20220050772
    Abstract: Incoming host data is programmed to a first set of data blocks indicated by a first cursor of a memory sub-system. The first set of blocks is associated with a first write mode. A determination is made that a second set of blocks associated with a second write mode is available to store the incoming host data prior to closing one or more of the first set of blocks. The incoming host data is programmed to the second set of blocks in view of a second cursor of the memory sub-system. A media management operation is performed to close the one or more of the first set of blocks.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Kevin R. Brandt, Cory M. Steinmetz
  • REGRESSION-BASED CALIBRATION AND SCANNING OF DATA UNITS
    Publication number: 20220050735
    Abstract: Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Inventors: Vamsi Pavan Rayaprolu, Harish R. Singidi, Ashutosh Malshe, Sampath K. Ratnam, Qisong Lin, Kishore Kumar Muchherla
  • RELOCATING DATA TO LOW LATENCY MEMORY
    Publication number: 20220027062
    Abstract: A processing device in a memory sub-system identifies a plurality of word lines at a first portion of a memory device, determines a respective error rate for each of the plurality of word lines, and determines that a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines satisfy a first threshold condition pertaining to an error rate threshold. The processing device further identifies a third word line of the plurality of word lines that is proximate to the first word line and the second word line and relocates data stored at the third word line to a second portion of the memory device, wherein the second portion of the memory device is associated with a lower read latency than the first portion of the memory device.
    Type: Application
    Filed: October 12, 2021
    Publication date: January 27, 2022
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Peter Feeley
  • Read window size
    Patent number: 11231982
    Abstract: A processing device in a memory system incrementally adjusts a center read voltage for a first block of a memory device by a first offset amount to generate an adjusted read voltage and causes the adjusted read voltage to be applied to the first block to determine an adjusted bit count associated with the adjusted read voltage. The processing device further determines whether a difference between the adjusted bit count and a previous bit count associated with a previous read voltage satisfies a first threshold criterion pertaining to an error threshold, and responsive to the difference between the adjusted bit count and the previous bit count not satisfying the first threshold criterion, determines a read window for the first block based on the previous read voltage.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: January 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jung Sheng Hoei, Peter Sean Feeley, Sampath K. Ratnam, Sead Zildzic, Kishore Kumar Muchherla