Abstract: A method for acquiring signals received from multiple users in a single burst groups signals by power and sequentially processes the signal groups. A received sum of a plurality of user signals received in a burst is stored, and the transmitted symbols for each signal within a first group of the stored signals is estimated. A modified set of signals is then determined that excludes the signals of the first group. From the modified set of signals, the method continues by canceling multiuser interference among signals within a second group, and estimating transmitted symbols for each signal within the second group. The first and second groups includes all signals within a power band that defines the group, and the first band represents a higher power band than the second. Such iterative processing may continue for sequentially lower power bands until all signals are processed. A receiver is also detailed.

Abstract: Disclosed is a method for acquiring a user signal from among several received from multiple users in a single burst. The method includes receiving a plurality of user signals in a single transmission burst, suppressing multiuser interference among at least some of the plurality of received signals, and determining a carrier frequency of at least one signal from among the interference suppressed plurality of received signals. Said signals may rotate due to a lack of synchronization while being equalized. Also described is a multiuser receiver for acquiring at least one user signal from among several user signals received from multiple users in a single burst.

Abstract: A method and apparatus for detecting a spread spectrum signal is described. Signals can be detected using correlation techniques. When a signal is detected, declaring of signal presence is inhibited for offsets of signal parameters from the parameters of the detected signal, where the offset corresponds to a known sidelobe of the spreading code. This helps to reduce false detections caused by sidelobes of the spreading code.

Abstract: A correlator despreads a P/N long code constructed from two or more constituent codes A, B, C having N, M and L elements respectively. In a third stage, L filter taps decorrelate elements of the third constituent code from the input received signal, leaving elements of code AB. The outputs of the third stage delay line are summed and input into a second stage delay line having M filter taps to decorrelate the elements of the second constituent code from the input to the second stage, leaving elements of code A. The outputs of the second stage delay line are summed and input to a first stage delay line having N filter taps. The output of the first stage delay line is summed and input into a shift register. An energy peak in the shift register indicates the phase of the P/N elements in the register is proper.

Abstract: A technique for scheduling transmissions for a plurality of transmitters in a TDMA network is described. The technique includes assigning guard time between each pair of successive transmitters, where the guard time is related to the propagation delay between the pair of successive transmitters. Total guard time is minimized by selecting an order of transmission for the plurality of transmitters to minimize the total guard time.

Abstract: A method for partitioning communication resource among multiple users partitions a portion of an available communication resource into a series of time-frequency slots, and allows multiple users to transmit in one of at least two available modes within a time-frequency slot. Preferably, one mode is time division of the time-frequency slot into time sub-slots, and another mode is code division of the time-frequency slot according to different spreading codes that spread an individual user's signal only within the subject time-frequency slot. Further details as to pilot signals, guard intervals, and payloads are described.

Abstract: A composite code is made for example by exclusive-OR'ing each real element of a first constituent code A with each element of a second constituent code B to obtain a basic composite code. To suppress autocorrelation, differing numbers of doping code elements are inserted between code segments made from combining each element of code A with an element of code B. A matched filter first stage removes from its input the A code and any doping code added to it, summing the elements of code A. A matched filter second stage removes from its input the B code and any doping code added at the second level. The summed elements of code B are the input to the first stage. Optionally, the summed elements of the doping code at any level may be delayed and summed with the elements of the A code in the first stage.

Abstract: A matched filter decorrelator is described for efficiently performing a carrier frequency search while despreading a P/N long code constructed from two or more constituent codes such as codes A, B, C. The received signal is phase rotated into a frequency bin and partially despread, preferably over all but one of the constituent codes. To despread the final constituent code, the partially despread signal is input in parallel into frequency bins, where a phase rotator sets each input to a different bin. The frequency bins are then despread in parallel over the final constituent code, and an energy peak in one accumulator indicates which bin is the carrier frequency. Alternatively, a Fourier transform could be used over each of the frequency bins. By partially despreading prior to division into carrier frequency bins, hardware and computational burden are reduced as compared to prior art decorrelators. The present invention is particularly apt for use with an acquisition burst in a secure network.

Abstract: A network synchronization method designed to provide synchronization of multiple networks and devices. This invention provides a specific method for determining which nodes are responsible for network synchronization as nodes fail or cannot see each other due to conditions on the network. This allows for fault tolerance in a network in which conditions change dynamically. In addition, this invention uses synchronization codes and network numbers to isolate separate networks using the same physical medium, thus allowing sharing of network resources.

Abstract: A circuit and method for correcting phase of a received phase modulated (PM) signal. The method uses k most recently received data bits, which alternate between in-phase I and quadrature Q bits, as an address for a lookup table 60. The lookup table outputs a phase figure 62 derived from a reconstructed waveform. When the most recent k bit is a Q bit, the complement 68 of the phase figure 62 is calculated to yield a phase correction. Otherwise, the phase figure is the phase correction, which is applied to adjust the phase of a delayed version of the received signal. The delayed, phase adjusted signal is then applied to correct the phase of a received signal. The circuit splits an input PM signal in parallel between a matched filter 54 and a delay block 76, 88. The matched filter output provides the input to a register 58 for storing the k data bits. The delay block holds the PM signal until it is input into a loop phase shifter 78 synchronously with the phase correction.

Abstract: A circuit and method for correcting timing of a received phase modulated signal. The method uses k most recently received data bits as an address for a lookup table 60. The lookup table includes reconstructed waveforms from which a timing weighing factor is determined. The received PM from time t1 is delayed, phase adjusted, and multiplied by the timing weighing factor, the product of which is used by a timing adjust block 50 to adjust timing of the PM signal at a time after t1. The circuit inputs a PM signal to a timing adjust block 50. The output is split between a matched filter 54 and a loop phase shifter 78. The matched filter feeds alternating I and Q bits into a register 58 that holds k data bits, which are used as an address for a lookup table 60. The output of the lookup table 60 becomes a timing weighing figure, which is multiplied 74 with an output of the loop phase shifter 78 and then input into the timing adjust block 50 for adjusting timing of a PM signal.

Abstract: A Time Division Duplex (TDD), Code Division Multiple Access (CDMA) communication system includes a plurality of Customer Premises Equipment (CPE) and an Access Point (AP) that communicate through RF links. A CPE contains a receiver baseband subsystem and a transmitter baseband subsystem, and further contains receiver circuitry operable during a receive period for receiving an RF carrier from the AP and for deriving a receiver tracking signal that is indicative of a frequency and phase shift between the received RF carrier and a reference signal. The receiver circuitry further includes a frequency to phase accumulator (FPA) and a digital phase shifter (DPS) for correcting the frequency and phase of a receiver baseband signal by an amount and in a direction indicated by the receiver tracking signal.

Abstract: A method and system for providing low cost narrow band digital power line communication using OFDM-like protocols to promote spectral diversity, reduce data loss, and provide higher data throughput. This invention provides a specific design to accommodate the requirements of a wide variety of communication applications and is adapted to make use of an AC power line communication within a building or facility without requiring dedicated hard wiring and does so with the advantages of OFDM but without the high costs of OFDM.

Abstract: A system for providing communications between a wide variety of communication devices using the AC power line within a building or facility without requiring dedicated hard wiring. This invention is designed specifically to accommodate such devices as gateways, PCs, telephone devices, RF equipment, home automation devices and audio-visual devices.

Abstract: An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Abstract: Users or subscribers of a spread spectrum synchronous communications system provide signals to the central station or base unit of that system, and receive signals therefrom. Proper synchronization among those users (and their signals) is needed to ensure proper operation of the system. To ensure proper synchronization among those users, the signal produced by each user is checked for presence and amount of any offset error. This is accomplished by using three despreaders for the signal for each user. For one such user, each such despreader for that user receives the spreading code for that user. However, the spreading code as received by any one such despreader is time-delayed with respect to the spreading code as received by the other two despreaders. Each such despreader receives the spreading code with a different amount of delay imposed on that spreading code. The outputs of the three despreaders are digitally combined (e.g. compared), or compared, to produce the offset estimate for that user.

Abstract: An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Abstract: An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Abstract: A method and apparatus for constructing a series of PN code sets that can be used for multirate synchronous and quasi-synchronous CDMA systems. The construction technique produces PN codes that are balanced, and that furthermore do not require any synchronization of neighboring base stations. The method is a non-recursive method that uses a permuted orthogonal matrix to modulate permuted orthogonal matrices to create PN codes that support multirate operation. Furthermore, the codes constructed using the method have very good spectral properties (if chosen properly) when the code length, n, is reasonably large.

Abstract: Apparatus and method for digital frequency discrimination are provided that only require one sample per data symbol (e.g. one bit for BPSK or 2 bits for QPSK). This is accomplished by determining the difference between the carrier phase error on successive data symbols. The difference in phase error is then used as an approximation to the derivative of the phase error, which is the frequency error between the carrier and the local oscillator of the receiver. An important advantage of this apparatus and method is that they allow the maximum symbol rate to be processed by the receiver for a given digital technology. In other words, maximum symbol rate can now be equal to the maximum clock rate of the digital technology, if so desired by the user. In contrast, conventional digital frequency discriminators limit the maximum symbol rate to one-half or one-fourth of the maximum clock rate for a given digital technology.