Abstract: A programmable second order loop filter is provided with first and second programmable scaling circuits arranged in parallel and having their outputs connected to first and second programmable one bit serial adders respectively. The output of the second programmable serial adder is coupled to the input of said first programmable serial adder and has its output coupled to the input of a programmable output stage so as to provide the ability to maintain the average quantization bit error to one-half of one bit of the least significant bit of the full loop filter width even though the output does not use or employ all of the significant bits.

Abstract: A present invention novel frequency-phase discriminator has input channels for real and imaginary data which are coupled to two programmable despreaders. The first despreader has its real and imaginary outputs coupled to individual programmable data rate filters which have their individual outputs coupled to a quadrant detector that generates a phase angle direction signal and sign magnitude. The second despread has its real and imaginary outputs connected through individual programmable inverters to data rate filters which have their individual outputs coupled to a quadrant selector that selects error signal data rate information from one of four quadrant axes signals. A command generator is programmably coupled to the output of the quadrant detector and to the input of the quadrant selector and provides a selection signal to the quadrant selector which produces a frequency error signal output employed in a frequency lock loop or in a phase lock loop.

Abstract: Apparatus is provided for detecting the presence of a periodically keyed random modulated signal source. Received signals are stepped down to an intermediate frequency and then applied to pairs of narrow bandpass filters. The output from pairs of the narrow bandpass filters are applied to mixers to provide difference frequency signals occurring at the clock rate of the periodically keyed random modulated signal. The clock signal is processed through recovery circuits including a detector and a comparator A signal is generated at the output of the comparator when the clock signal is detected above the background noise and interference, thus, indicating the presence of a periodically keyed random modulated signal source.

Abstract: In a receiving apparatus for detecting the presence or absence of periodically keyed random modulated signals, there are provided a pair of separate and distinct detection channels. One channel produces a real signal having clock line components and the other channel produces a decorrelated imaginary signal having no clock line components. The real and imaginary signals having carrier wave interference signals are processed in a Fourier transform device and a post processor to cancel out the carrier wave interference signals and to provide only a clock signal output when periodically keyed random modulated signals are being received.

Abstract: A coherent pseudonoise code (PN) tracking loop is provided with apparatus for sensing the absence of PN transition in the incoming data stream to the tracking loop and for switching OFF the data stream to prevent phase error distortion and inherent noise from entering the tracking loop which could be sensed as false or incorrect phase error signals. The apparatus includes a transition switch in the incoming data stream that is responsive to transition gate control logic coupled to the output of the PN replica generator in the tracking loop for switching OFF the incoming data stream when no PN transitions are occurring.

Abstract: A novel digital phase shifter is provided for accomplishing digital phase shifting without the requirement of complex multiplication. The phase shifter includes buffer registers for receiving and storing the inphase and quadrature components of a complex number and for storing in a phase command register the information indicative of the phase shift to be accomplished. The phase shifting apparatus comprises a command map for generating a plurality of plus or minus phase shift command bits. A plurality of plus or minus phase shift registers are coupled to the phase shift command bits for performing plus or minus phase shifts of predetermined angles that diminish by a factor of approximately one-half from the previous phase shift angle.

Abstract: A method of rapidly reacquiring a pseudonoise spread spectrum coded signal after short outages includes calculating the new positions of the moving stations relative to the old positions of the moving stations and for determining the accurate displacement and the accurate direction the platforms have moved in their new direction after a short time outage. The method includes calculating a triangle which includes the displacement between the moving stations' old position and the moving stations new position and the included angle between the direction of movement and the line of sight between said moving platforms at the time of outage. A range displacement adjustment is calculated on the basis of the triangle for each moving station and the range factor resulting from this calculation is applied to the PN generators of the receiver and transmitter in each of the moving stations to independently adjust for each station's movement.

Abstract: A variable rate near perfect rectangular matched filter is provided with a low pass filter coupled to the input symbol data stream. The output of the filter is coupled to a sampler and the output of the sampler is coupled to an analog to digital converter to provide digital samples indicative of the data stream at a time occurring between input data symbols. The output of the analog to digital converter is applied to a digital adder which has a filter correction input factor to adjust the output of the digital adder so that the digital samples approximate very closely the output of a perfect rectangular matched filter.

Abstract: The present invention is concerned with an apparatus and a method of jumping a composite PN code from a current phase position to a desired predetermined phase position so as to enhance acquisition of a composite PN code. The apparatus includes a plurality of individual PN code generators which are connected to a code combiner to produce a composite PN code. Each of the individual PN code generators is driven by its own timing gate for supplying synchronized clock pulses to its own PN code generator. A master clock is connected to a timing gate before being connected to the individual PN code generators. An inhibit input at each of the individual timing gates is provided so that the individual PN generators may be inhibited a predetermined number of clock pulses which causes the PN code generated to be inhibited and has the effect of jumping the PN code a desired number of phase positions.

Abstract: A feedback loop circuit that may be used for Fourier Transform analysis, for carrier acquisition, or for other related purposes, sums the inputs signal, passes it through a delay line to provide an output signal, samples a portion of the output signal in a feedback path, mixes the supplied feedback signal with a first oscillator signal that is several times larger than the center frequency of the allowed input signal bandwidths, eliminates the low sideband frequencies of this mixed signal, mixes this signal with a second local oscillator signal, the frequency of which is lower than the frequency of the first local oscillator by approximately the inverse of the delay time of the input signal, filters out the high sideband frequencies of this signal and combines the remaining feedback signal (either by summation or subtraction) with the input signal.

Abstract: A non-coherent receiving system is provided with a novel triple-bit matched filter detector system which provides two outputs indicative of the data stream being detected. A preliminary or soft decision is made concerning the state of the bits in the data stream. One of the outputs provides a best estimate of state of the data bit being detected and the other output provides the second best estimate of the state of the data bits being detected. The incoming data stream is processed and modified as it is shifted through a plurality of shift registers in real time employing the data bits subsequently detected. A controller is provided to make a plurality of predetermined evaluations of the state of the bits in the data stream and to provide a final or hard decision of the correct state of the data bits previously detected.

Abstract: The present invention provides a spread spectrum waveform encoded altimeter. Spread spectrum carrier wave signals which are transmitted and later received are processed in a novel edge detecting apparatus which includes a plurality of individual detectors. A pair of detectors are provided to detect an early chip or signal. Another pair of detectors are provided to detect a late chip or signal. There is also provided a pair of edge chip detectors for detecting the center or locked on chip signal. Logic circuits are employed to sum the voltage signals from the detectors and to provide a control signal capable of adjusting a tracking generator to enable it to lock on to the received signal. An altimeter counter is provided which is started by a unique chip in the transmitted signal and stopped when the same unique chip is detected in the receiving and tracking loop.