Abstract: Disclosed are methods for acquiring a forward channel in a point-to-multipoint CDMA system. One method includes the steps of (a) despreading a received CDMA signal with a first pn code that is known to be present in the received CDMA signal and obtaining a first measure of received signal level; (b) despreading the received CDMA signal with a second pn code that is known not to be present in the received CDMA signal and obtaining a second measure of received signal level; and (c) synchronizing to a desired channel using a difference between the first and second signal levels. In this method the first step of despreading despreads a continuously transmitted side-channel, and the step of synchronizing synchronizes to the side-channel. Also, the step of obtaining a first measure of received signal level obtains a correlation peak, and the step of obtaining a second measure of received signal level obtains a correlation null.

Abstract: Apparatus and method are provided that can be advantageously included in a timing phase-locked loop for finally adjusting the period of a timing signal being controlled by that loop. The loop filter receives the timing signal and generates a loop error signal indicative of whether the period of the timing signal should be held the same, increased or decreased. A strobe signal is also generated each time that the timing signal is to be so corrected. The error signal and strobe signal are provided to a function generator such as a state machine. Each time that the function generator is strobed by the strobe signal, it produces a count signal whose value is representative of N, N+C or N-C, where N and C are integers and C represents a preset desired increment of change for the timing signal per strobe, i.e. the fineness of the adjustment of the timing signal. When not strobed by the strobe signal, the state machine produces a count signal of value N.

Abstract: Users or subscribers of a spread spectrum synchronous communications system provide signals to the central station or base unit of that system, and receive signals therefrom. Proper synchronization among those users (and their signals) is needed to ensure proper operation of the system. To ensure proper synchronization among those users, the signal produced by each user is checked for presence and amount of any offset error. This is accomplished by using three despreaders for the signal for each user. For one such user, each such despreader for that user receives the spreading code for that user. However, the spreading code as received by any one such despreader is time-delayed with respect to the spreading code as received by the other two despreaders. Each such despreader receives the spreading code with a different amount of delay imposed on that spreading code. The outputs of the three despreaders are digitally combined (e.g. compared), or compared, to produce the offset estimate for that user.

Abstract: Disclosed are methods and apparatus for use in a synchronous CDMA communications system (10) that employs orthogonal pn spreading codes. The methods are intended for synchronizing transmissions from a subscriber unit (SU 14) to a radio base unit (RBU 12), and include the steps of: (a) transmitting individual ones of a plurality of bursts from the SU to the RBU, each burst being transmitted with a different pn spreading code timing alignment; (b) receiving individual ones of the plurality of bursts with the RBU and determining a power estimate of each received burst; and (c) in response to a determined power estimate of one of the bursts exceeding a threshold, sending a message from the RBU to the SU. The message indicates that the SU is to use for subsequent transmissions the pn spreading code timing alignment that was employed when transmitting the burst that exceeded the threshold.

Abstract: Disclosed are methods for acquiring a forward channel in a point-to-multipoint CDMA system. One method includes the steps of (a) despreading a received CDMA signal with a first pn code that is known to be present in the received CDMA signal and obtaining a first measure of received signal level; (b) despreading the received CDMA signal with a second pn code that is known not to be present in the received CDMA signal and obtaining a second measure of received signal level; and (c) synchronizing to a desired channel using a difference between the first and second signal levels. In this method the first step of despreading despreads a continuously transmitted side-channel, and the step of synchronizing synchronizes to the side-channel. Also, the step of obtaining a first measure of received signal level obtains a correlation peak, and the step of obtaining a second measure of received signal level obtains a correlation null.

Abstract: A low radar cross section lens antenna having high gain is disclosed. A spherical lens having a dielectric radial gradient focuses planar RF energy coupled thereto onto a focal point on the surface of a lens located diametrically opposite from the first intersection of the plane wave and the lens. The lens partially encloses a wedge shaped RF absorbing portion having the edge of the wedge passing through the center of the lens. The lens is partially surrounded by a second RF absorbing portion having a bowl-like shape. An antenna feed having its aperture located adjacent the surface of the lens is mounted to rotate about an axis lying substantially along the edge of said wedge shaped absorbing portion. Elevation rotation means is provided to rotate the feed antenna within a slot contained within the second RF absorbing portion.

Abstract: A multipoint-to-point CDMA communication system comprises a plurality of CDMA transmitting stations and a single CDMA receiving station, all of which are intercoupled to each other over one CDMA channel and one feedback channel. On the one CDMA channel, the plurality of CDMA transmitting stations simultaneously send respective CDMA signals to the receiving station. In the receiving station, respective time differences are measured between a reference clock signal and the spreading codes in the CDMA signals from each of the CDMA transmitting stations; and these time differences are indicated in respective error signals which the CDMA receiving station sends on the feedback channel to each of the CDMA transmitting stations. Each CDMA station responds to its error signals by time shifting its spreading code such that it arrives in the receiving station in synchronization with the reference clock signal.

Abstract: A multipoint-to-point CDMA communication system comprises a plurality of CDMA transmitting stations and a single CDMA receiving station, all of which are intercoupled to each other over one CDMA channel and one feedback channel. On the one CDMA channel, the plurality of CDMA transmitting stations simultaneously send respective CDMA signals to the receiving station. In the receiving station, respective time differences are measured between a reference clock signal and the spreading codes in the CDMA signals from each of the CDMA transmitting stations; and these time differences are indicated in respective error signals which the CDMA receiving station sends on the feedback channel to each of the CDMA transmitting stations. Each CDMA station responds to its error signals by time shifting its spreading code such that it arrives in the receiving station in synchronization with the reference clock signal.

Abstract: Apparatus for rapidly acquiring a high performance gain long PN code having a preamble header in real time includes appratus for rapid acquiring and tracking a short PN code in said preamble header and further includes apparatus for demodulating and tracking a long PN code which follows said preamble header. After acquiring the short PN code, the short PN replica code is applied to the long code demodulation and tracking apparatus. The short PN code is employed to synchronize the long code demodulation and tracking apparatus by detecting the time of occurrence of a sync word in said preamble header and is employed to generate a switch point signal and switch from a short PN replica code to a long PN replica code at the input to the long code demodulation and tracking device in real time.

Abstract: A programmable randomly tunable digital demodulator is provided with a carrier recovery loop and a PN code clock recovery loop each having a programmable digital loop filter coupled in series therein. Each digital loop filter is controlled by a timing control which is capable of controlling the carrier frequency tuning and the PN tuning frequency under the control of a microprocessor. A replica PN generator is programmed to produce an epoch signal when the transmitted carrier frequency and/or chipping rate is varied in a pseudorandom manner and is coupled to the timing controls so that the modulator replicates the received variable rate signals.

Abstract: A high chipping rate digital demodulator circuit is coupled to the output of an analog front end communications receiver and comprises a low pass filter in each channel of the receiver. The filtered output is coupled to a plurality of parallel branches each having an analog to digital converter which converts a portion of an analog sample to digital format and effectively reduces the system clock rate by a ratio of the number of parallel branches. One set of parallel branches is coupled to an early-late clock error detector circuits and another set of parallel branches is coupled to data signal detector circuits and then combined before being applied to a clock error processing channel and a data signal phase error channel which maintains the lower clock rate of the parallel branches.

Abstract: A novel PN code acquisition and demodulation circuit comprise an analog receiver coupled to an analog to digital converter. The digital output of the converter is passed through an N chip width parallel correlator. The parallel outputs are coherently accumulated to provide N soft decision data values one of which is indicative of the proper replica code for locking onto the data. All of the soft decision data values are stored in a high speed memory in real time. Subsequently non-coherent accumulated soft decision data is employed to detect the proper PN replica code. Logic selection means accesses the soft decision data stored in the high speed memory in non real time and selects the best estimate for the soft decision data and applies the soft decision data to a demodulator in non-real time to recover the hard data encoded in the received PN coded data.

Abstract: A high PN code rate receiving system is provided for receiving, recovering and tracking a high rate PN composite code comprising a low rate PN code combined with a high rate PN code and wherein the receiving system comprises a broad band receiver for receiving the high rate PN composite code and further includes a data recovery channel and a tracking loop channel. The data recovery channel comprises a high rate mixer and a low rate mixer for removing the high data rate component code and the low data rate component code to provide a low data rate data stream. The tracking loop channel comprises a high rate early-late tracking system for producing a high rate error signal and further comprises a low rate portion of the tracking loop for producing a low rate error signal which is combined with the data output to provide a clock error signal.

Abstract: A novel range based acquisition system includes a receiver for receiving PN encoded signals coupled to a novel range based variable dwell correlator which detects and acquires uniquely timed received transmitter PN encoded signals employing different search dwell times for each of the estimated ranges from which the receiver transmitted PN encoded signals are being propagated so as to enhance the speed of acquisition of said PN encoded signals.

Abstract: A novel programmable digital gain controller is provided for the automatic gain control loop of a communications receiver. The digital gain controller comprises a pair of digital detectors coupled to the real and imaginary components of a data stream for providing digital data magnitude output signals which are coupled to an adder whose output is coupled to a first input of a comparator having a second input coupled to a predetermined reference level command. The output of the comparator generates a digital error signal which is coupled to the input of a programmable gain accumulator having a second input proportional gain command so as to provide at the output of the programmable gain accumulator a digital gain command which may be coupled to a variable gain controlled amplifier which is connected in the input data stream of the channel of a communications receiver to provide a predetermine amplifier output level.

Abstract: A time error signal generator of the type employed in symbol time tracking loops is provided with a pre-accumulate and scale circuit for receiving an input data stream which is applied to a digital early sample-late sample circuit for generation an error signal indicative of a time magnitude difference between the analog transition time of the data and the chip strobe time multiplied by the sign of the data. The output of the early sample-late sample circuit is applied to a second accumulate and scale circuit for generating an accumulated error signal which is applied to an inverter. The inverter is provided with a decision directed tracking input indicative of the sign of the data sample and is employed to invert the accumulated error signal when the sign of the analog data is negative.

Abstract: A novel programmable digital acquisition and tracking controller is coupled to the input signal level from the demodulator of a communications receiver and provides programmable signal level threshold detectors and detection intervals adapted to produce an output signal which is indicative of the correlation between the received PN code and the locally generated PN code as compared against a programmable threshold. The programmable detector logic is capable of detecting acquisition correlation and tracking correlation and can optionally inform an external microprocessor of the correlation level so as to implement a wide variety of acquisition, tracking and reacquisition algorithms as well as optional AM demodulation.

Abstract: A novel accumulate and scale circuit is provided with an input accumulator which is only as wide as the input data stream. Additional most significant bits are generated to extend the output of the accumulate and scale circuit by providing and an up and down counter having a number of most significant bit stages. The adder stages of the input accumulator have their carry and borrow outputs coupled to the up and down counter for generating additional most significant bits.

Abstract: A six channel programmable digital demodulator of the type designed to be manufactured as an integrated circuit with other components comprises a code channel, a level channel and a phase channel each of which includes two accumulate and scale circuits. Each of the accumulate and scale circuits is connected to an I or a Q channel of the data which has been despread after being received from the communications receiver. The outputs of two of the accumulate and scale circuits are applied to a two to one multiplexor which is controlled by a command generator to provide a selectable output defining a clock error signal. The remaining four accumulate and scale circuits are connected to a first four to one multiplexor to provide a selectable output defining a clock error signal. The same four remaining outputs from said accumulate and scale circuits are connected to a second four to one multiplexor having an output defining a carrier error signal.

Abstract: A programmable digital gain accumulator is provided with a digital accumulator having approximately the same number of significant bits as the input data stream. The most significant bit of the input data stream is a sign bit coupled to a series cascade of flip-flops providing a selectable plurality of flip-flop delay times. The carry output of the accumulator is coupled to an input up/down counter having its output coupled to a multiplexor capable of selecting one of the carry outputs of the input up/down counter. The up or down count is controlled by the sign bit input from the sign bit delay circuit. The output of the multiplexor is inputted to an output up/down counter whose parallel output is the parallel synchronous digital gain command signal for direct use by a utilization device. The up or down count of the output up/down counter is controlled by a delayed sign input from the sign bit delay circuit.