Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.

Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

Abstract: A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.

Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.

Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.

Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.

Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

Abstract: A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.

Abstract: A device includes a phosphide-containing structure, a dopant source layer and a conductive contact. The phosphide-containing structure has a first chemical element in a compound with phosphorus. The dopant source layer is over the phosphide-containing structure and has a second chemical element the same as the first chemical element. The conductive contact is over the dopant source layer.

Abstract: A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.

Abstract: A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.

Abstract: A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.

Abstract: A method includes providing a black phosphorus (BP) layer over a substrate, forming a dopant source layer over the BP layer, annealing the dopant source layer to drive a dopant from the dopant source layer into the BP layer, and forming a conductive contact over the dopant source layer.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.

Abstract: A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other.

Abstract: A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.