Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a substrate; a gate stack over the substrate. The gate stack includes a ferroelectric layer; a first dielectric material layer; and a first conductive layer. One of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with fixed charge. The semiconductor device further includes source and drain features formed on the substrate and disposed on sides of the gate stack.

Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.

Abstract: Three-dimensional (3D) transistors and methods of manufacturing thereof include a first semiconductor fin extending over a substrate. The first semiconductor fin has a vertical recess extending from a first sidewall of the first semiconductor fin toward a second sidewall of the first semiconductor fin opposite the first sidewall. A distance between two opposing sidewalls of the vertical recess decreases as the vertical recess extends toward the second sidewall of the first semiconductor fin. The device further includes a vertically recessed channel region between the second sidewall of the first semiconductor fin and a bottom of the vertical recess, source/drain (S/D) regions at opposite ends of the vertically recessed channel region, and a gate stack over the vertically recessed channel region.

Abstract: Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a source structure in a semiconductor substrate. The semiconductor device structure also includes a channel layer over the semiconductor substrate. A first portion of the channel layer covers a portion of the source structure. A second portion of the channel layer laterally extends away from the source structure. The semiconductor device structure further includes a drain structure over the semiconductor substrate. The drain structure and the source structure have different conductivity types. The drain structure adjoins the second portion of the channel layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A first gate electrode layer is formed over a substrate. A first gate dielectric layer is formed over the first gate electrode layer. A first channel layer is formed over the first gate dielectric layer. An isolation layer is formed over the first channel layer. A second channel layer is formed over the isolation layer. A second gate dielectric layer is formed over the second channel layer. The second gate dielectric layer, the second channel layer, the isolation layer and the first channel layer are patterned to form a first opening, the first opening extending through the first gate dielectric layer, the second channel layer and the isolation layer, and into the first channel layer. A first source/drain region is formed in the first opening.

Abstract: Semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer. A source/channel/drain stack is formed over the first gate stack, wherein the source/channel/drain stack comprises one or more 2D material layers. A second gate stack is formed over the source/channel/drain stack, wherein the second gate stack comprises a second ferroelectric layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A source/drain electrode stack is formed over a substrate, wherein the source/drain electrode stack comprises a first source/drain electrode and a second source/drain electrode. A source/channel/drain layer is formed on a sidewall of the source/drain electrode stack, wherein the source/channel/drain layer comprises a 2D material. A gate stack is formed on the source/channel/drain layer.

Abstract: A semiconductor device and method of manufacturing are presented in which features of reduced size are formed using an irradiated mask material. In an embodiment a mask material that has been irradiated with charged ions is utilized to focus a subsequent irradiation process. In another embodiment the mask material is irradiated in order to reshape the mask material and reduce the size of openings formed within the mask material. Through such processes the limits of photolithography may be circumvented and smaller feature sizes may be achieved.

Abstract: The present disclosure relates to a tunnel FET device with a steep sub-threshold slope, and a corresponding method of formation. In some embodiments, the tunnel FET device has a dielectric layer arranged over a substrate. A conductive gate electrode and a conductive drain electrode are arranged over the dielectric layer. A conductive source electrode contacts the substrate at a first position located along a first side of the conductive gate electrode. The conductive drain electrode is arranged at a second position located along the first side of the conductive gate electrode. By arranging the conductive gate electrode over the dielectric layer at a position laterally offset from the conductive drain electrode, the conductive gate electrode is able to generate an electric field that controls tunneling of minority carriers, which can change the effective barrier height of the tunnel barrier, and thereby improving a sub-threshold slope of the tunnel FET device.

Abstract: A method for manufacturing a semiconductor device comprising two-dimensional (2D) materials may include: epitaxially forming a first two-dimensional (2D) material layer over a substrate; calculating a mean thickness of the first 2D material layer; comparing the mean thickness of the first 2D material layer with a reference parameter; determining that the mean thickness of the first 2D material layer is not substantially equal to the reference parameter; and after the determining, epitaxially forming a second 2D material layer over the first 2D material layer.

Abstract: Resistive random-access memory (RRAM) devices and methods of manufacturing thereof are disclosed. A device comprises a first transparent conducting oxide (TCO) layer and a second TCO layer over the first TCO layer. The device further comprises a first dielectric layer between the first TCO layer and the second TCO layer, a second dielectric layer between the second TCO layer and the first dielectric layer, and a metal layer between the first dielectric layer and the second dielectric layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.

Abstract: Three-dimensional (3D) transistors and methods of manufacturing thereof include a first semiconductor fin extending over a substrate. The first semiconductor fin has a vertical recess extending from a first sidewall of the first semiconductor fin toward a second sidewall of the first semiconductor fin opposite the first sidewall. A distance between two opposing sidewalls of the vertical recess decreases as the vertical recess extends toward the second sidewall of the first semiconductor fin. The device further includes a vertically recessed channel region between the second sidewall of the first semiconductor fin and a bottom of the vertical recess, source/drain (S/D) regions at opposite ends of the vertically recessed channel region, and a gate stack over the vertically recessed channel region.

Abstract: Semiconductor devices and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a semiconductor device may include: patterning a substrate to have a first region and a second region extending from the first region of the substrate; depositing an isolation layer over a surface of the first region of the substrate; and epitaxially forming source/drain regions over the isolation layer and adjacent to sidewalls of the second region of the substrate.

Abstract: A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [?2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric.

Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.

Abstract: Semiconductor devices and methods of forming the same are provided. A first gate electrode layer is formed over a substrate. A first gate dielectric layer is formed over the first gate electrode layer. A first channel layer is formed over the first gate dielectric layer. An isolation layer is formed over the first channel layer. A second channel layer is formed over the isolation layer. A second gate dielectric layer is formed over the second channel layer. The second gate dielectric layer, the second channel layer, the isolation layer and the first channel layer are patterned to form a first opening, the first opening extending through the first gate dielectric layer, the second channel layer and the isolation layer, and into the first channel layer. A first source/drain region is formed in the first opening.

Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.