Abstract: A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H2SO4, H3PO4, HF and H2O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.

Abstract: A floating gate having a first and second end region, each of which are positioned adjacent to a corresponding lateral end of the floating gate. A middle region is positioned laterally towards a middle of the floating gate relative to the first and second end regions. The first end region, the middle region and the second end region are formed of a same material during a single fabrication step, and the middle region formed has a thickness which is less than a thickness of the first or second end regions. This invention further includes a method for forming a contoured floating gate for use in a floating gate memory cell.

Abstract: The invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end region and the second lateral end region. The thickness of the floating gate decreases continuously from at least one of the first or second lateral end regions to the middle region. This invention also provides for a method of forming a contoured floating gate for use in a floating gate memory cell.

Abstract: A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer, and an etch stop layer. A photoresist masking process is performed on the multilayer structure to define gates of the nonvolatile memory device. A spacer layer is then deposited and etched back to form sidewall spacers adjacent the gates. The width of the sidewall spacers is used to define the width of the source and drain regions, and the width of trenches between the gates. Trenches are formed using a high selectivity etch which etches through the substrate faster than the sidewall spacers and the etch stop layer. A conductive layer is formed over the area of the device and etched to form the reduced resistance diffusion regions and the desired trench configuration. The trenches are then filled with an insulating material.

Abstract: Apparatus is provided for use in carrying out liquid-liquid extraction techniques, which apparatus includes an extraction column containing a unique solvent sorbing packing material, namely a plurality or bundle of elongated fibrous strands having first and second end portions, the strands being capable of sorbing a desired solvent; the apparatus also includes a separation zone in communication with the second end of the plurality of fibrous strands, means for feeding a first or heavy solvent phase through the bundle of fibrous strands so as to be sorbed by said strands, and subsequently into the separation zone, means for feeding a second or light solvent phase into the separation zone and thence through the annular spaces of the column, around the fibrous strands contained therein, means for recovering the light solvent phase from the first end of said bundle and means for recovering said heavy solvent phase from said separation zone.