Patents by Inventor Samuel D. Naffziger

Samuel D. Naffziger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11073888
    Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: July 27, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
  • Publication number: 20200379544
    Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
  • Patent number: 10060955
    Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: August 28, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Aaron J. Grenat, Robert A. Hershberger, Sriram Sambamurthy, Samuel D. Naffziger, Christopher E. Tressler, Sho-Chien Kang, Joseph P. Shannon, Krishna Sai Bernucho, Ashwin Chincholi, Michael J. Austin, Steven F. Liepe, Umair B. Cheema
  • Patent number: 9727435
    Abstract: A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 8, 2017
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Samuel D. Naffziger, Suresh B. Periyacheri
  • Patent number: 9710034
    Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: July 18, 2017
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Samuel D. Naffziger, Michael Osborn, Sebastien Nussbaum
  • Patent number: 9671767
    Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes one or more processing units each of which operates with respective operating parameters. One or more temperature sensors are included to measure a temperature of the one or more processing units during operation. When the measured temperature exceeds a threshold, a power manager on the chip determines a temperature headroom utilizing temperature values based on worst-case ambient temperature. When the measured temperature does not exceed the threshold, the power manager determines the temperature headroom utilizing at least one temperature value based on room ambient temperature. Following, the power manager adjusts the respective operating parameters based on at least the temperature headroom.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: June 6, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Samuel D. Naffziger, Benjamin D. Bates, Praveen K. Dongara
  • Patent number: 9575553
    Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: February 21, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seng Oon Toh, Edward J. McLellan, Stephen V. Kosonocky, Michael Leonard Golden, Samuel D. Naffziger
  • Publication number: 20160179186
    Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Seng Oon Toh, Edward J. McLellan, Stephen V. Kosonocky, Michael Leonard Golden, Samuel D. Naffziger
  • Publication number: 20150378411
    Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 31, 2015
    Inventors: Aaron J. Grenat, Robert A. Hershberger, Sriram Sambamurthy, Samuel D. Naffziger, Christopher E. Tressler, Sho-Chien Kang, Joseph P. Shannon, Krishna Sai Bernucho, Ashwin Chincholi, Michael J. Austin, Steven F. Liepe, Umair B. Cheema
  • Publication number: 20150331433
    Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes one or more processing units each of which operates with respective operating parameters. One or more temperature sensors are included to measure a temperature of the one or more processing units during operation. When the measured temperature exceeds a threshold, a power manager on the chip determines a temperature headroom utilizing temperature values based on worst-case ambient temperature. When the measured temperature does not exceed the threshold, the power manager determines the temperature headroom utilizing at least one temperature value based on room ambient temperature. Following, the power manager adjusts the respective operating parameters based on at least the temperature headroom.
    Type: Application
    Filed: May 14, 2014
    Publication date: November 19, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Samuel D. Naffziger, Benjamin D. Bates, Praveen K. Dongara
  • Patent number: 9182803
    Abstract: A method and apparatus for load step, or instantaneous current spike, mitigation are provided. In the method and apparatus, load steps are mitigated if a computer system a whole is lightly load, which may be determined by the power consumption of the computer system. Further, load steps are mitigated if a number of processor cores capable of inducing a load step is higher than a threshold. The Advanced Configuration and Power Interface (ACPI) performance state of the cores is used to determine a core's potential for generating a load step. A processor core is instructed to mitigate load steps if conditions are met for the mitigation.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: November 10, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Samuel D. Naffziger, John P. Petry, Kiran Bondalapati
  • Publication number: 20150286550
    Abstract: A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Samuel D. Naffziger, Suresh B. Periyacheri
  • Publication number: 20150268707
    Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Samuel D. Naffziger, Michael Osborn, Sebastien Nussbaum
  • Publication number: 20150268713
    Abstract: The operating point of a processing unit is controlled based on the power consumption (i.e., the rate of energy consumption) associated with a workload, wherein low power consumption may indicate short-duration workloads with idle phases and high power consumption may indicate long, sustained workloads. Energy credits are accumulated while a drain rate of a battery is lower than a threshold drain rate and the energy credits are consumed while the drain rate is higher than the threshold drain rate. The operating point of the processing unit may be increased from a first operating point to a second operating point in response to the energy credits exceeding a first threshold. The operating point of the processing unit may be decreased from the second operating point to the first operating point in response to the energy credits falling below a second threshold.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 24, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ashish Jain, Alexander J. Branover, Samuel D. Naffziger, Dongyuan Zhan
  • Patent number: 9092219
    Abstract: A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: July 28, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Samuel D. Naffziger, Suresh B. Periyacheri
  • Patent number: 9052359
    Abstract: A method and system for varying sampling frequency to avoid software harmonics when sampling digital power indicators are described herein. A power monitor may repetitively sample, at a variable sampling rate based on a variable delay time, multiple signals of an IC device to obtain energy values. The variable delay time may be based on a pseudo-random value or a predictable value. The variable delay time may indicate a number of delay cycles that may be inserted between the repetitive samples of the energy values. The variable number of delay cycles between energy value samples may produce a variable sampling rate. A variable sampling rate may avoid alignment with software harmonics which can cause an inaccurate representation of power consumption. The multiple samples obtained by repetitively sampling energy value for the portion of the IC may be summed to generate a cumulative energy value for the portion of the IC.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: June 9, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Samuel D. Naffziger, Suresh B. Periyacheri
  • Patent number: 9052885
    Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 9, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Samuel D. Naffziger, Michael Osborn, Sebastien Nussbaum
  • Patent number: 8975936
    Abstract: An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 10, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Visvesh S. Sathe, Samuel D. Naffziger
  • Patent number: 8942932
    Abstract: Techniques are disclosed relating to determining power consumption of an integrated circuit. In one embodiment, an integrated circuit is disclosed that includes a power monitor unit configured to receive a temperature of the integrated circuit, and to determine an estimate of power consumed by transistor leakage of the integrated circuit based on the received temperature. In one embodiment, to determine the estimate, the power monitor unit is configured to multiply a base value and a scaling factor that is adjusted based on the received temperature. In some embodiments, the power monitor unit is configured to receive performance state information of the integrated circuit, and to determine an estimate of power consumed by transistor leakage of the integrated circuit based on the performance state information.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: January 27, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Samuel D. Naffziger
  • Patent number: 8854100
    Abstract: A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 7, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Visvesh S. Sathe, Samuel D. Naffziger, Srikanth Arekapudi