Abstract: A system and method for efficient reporting of power usage. A power reporting unit within a processor receives a power consumption number once every sample interval from a power monitor. The power monitor determines a power consumption number based on data corresponding to activity levels of one or more functional blocks within the processor. This data corresponds to each of a number of sampled signals within the one or more functional blocks rather than temperature. Thus, the data is independent of environment temperature variations. An average power consumption number is computed based on received power consumption numbers for a running time interval, wherein the running time interval is larger than the sample interval. This value is conveyed to an external agent, such as a controller for a data center rack system. Responsive to receiving and processing the average power consumption number, the external agent may perform one or more actions.

Abstract: An apparatus comprising an integrated circuit on a VLSI die, and an embedded micro-controller constructed on the VLSI die, the micro-controller adapted to monitor and control the VLSI environment to optimize the integrated circuit operation. Another embodiment of the invention is directed to a method for monitoring and controlling an integrated circuit comprising providing an embedded micro-controller on a same VLSI die as the integrated circuit, monitoring and controlling a VLSI environment of the integrated circuit with the embedded micro-controller.

Abstract: A system and method for real-time power estimation. A core may be divided into units. Each unit is simulated to achieve a real power consumption characterization. The power consumption is sampled. Statistical analysis is performed that assumes the core has node capacitance switching behavior that is approximated by a stationary random process with a Poisson distribution. The statistical analysis determines the number of samples to take during a sample interval. The operational frequency, sample interval, and number of samples are used to determine the number of signals to sample. Signals are chosen that have a high correlation with the node capacitance switching behavior, such as clock enable signals on the last stage of a clock distribution system. Weights with tuned values are assigned to each sampled signal. Sampling occurs during every predetermined number of clock cycles. The weights of asserted sampled signals are summed in order to determine a repeatable power estimation value.

Abstract: A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with available source data, the corresponding weight values are summed together to produce a local current consumption value and this value is summed with any existing global current consumption values from corresponding schedulers of other processor cores yielding an activity event. The activity event is stored. Hashing functions within the scheduler are used to determine both a recent and an old activity average using the calculated activity event and stored older activity events.

Abstract: Devices and methods for managing power on a module are disclosed herein. In one embodiment, a module comprises a first die; a second die; and a power manager. The power manager monitors the power requirements of the first die and the second die and allocates power to the first die and the second die based on the power requirements.

Abstract: A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. Rather than provide a single clock to flip-flop circuits on a semiconductor chip, split clocks are used. A flip-flop receives a master clock signal for a master latch and receives a separate slave clock signal for a slave latch. Master and slave clock gater circuits are coupled to a global clock distribution system and the local flip-flops. The master clock gater circuit receives a delay control signal used to select a delay, wherein the selected delay determines an additional amount of time the master clock signal transitions after the slave clock signal transitions. The use of the delayed master clock on the semiconductor chip may allow a timing path to have more computation time without increasing the clock cycle time. Further, the delay may be chosen to fix timing paths in post-silicon.

Abstract: A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived from an ungated input clock signal and a clock gating condition. The clock gating condition determines when an input data signal of the flip-flop and the stored internal state of the slave latch have the same logic value, such as only a logic low value. If they have the same value, toggling of the ungated input clock signal is not received by the slave latch, signal switching of internal nodes of the slave latch is reduced, and power consumption is reduced.

Abstract: A method for controlling power consumption while maximizing processor performance. The method includes, for a time interval of operation in a first operational state, determining an amount of power consumed during by one or more cores of a processor, calculating, a power error based on the amount of power consumed in the time interval, obtaining a power error term for the interval by adding the power error to a power error term from a previous time interval, and comparing the power error term to at least a first error threshold. If the power error term is outside a range defined at least in part by the first error threshold, the method exits the first operational state and enters a second operational state. If the power error term is within the range defined at least in part by the first error threshold, operation continues in the first operational state.

Abstract: A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device.

Abstract: Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a working power limit evaluator that determines a working power limit as a function of at least one performance factor associated with variations that affect performance of the integrated circuit. The system may further comprise a power management system that varies power of the integrated circuit based on the working power limit and an actual power of the integrated circuit to maintain a substantially constant performance.

Abstract: A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with available source data, the corresponding weight values are summed together to produce a local current consumption value and this value is summed with any existing global current consumption values from corresponding schedulers of other processor cores yielding an activity event. The activity event is stored. Hashing functions within the scheduler are used to determine both a recent and an old activity average using the calculated activity event and stored older activity events.

Abstract: A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived from an ungated input clock signal and a clock gating condition. The clock gating condition determines when an input data signal of the flip-flop and the stored internal state of the slave latch have the same logic value, such as only a logic low value. If they have the same value, toggling of the ungated input clock signal is not received by the slave latch, signal switching of internal nodes of the slave latch is reduced, and power consumption is reduced.

Abstract: A system and method for real-time power estimation. A core may be divided into units. Each unit is simulated to achieve a real power consumption characterization. The power consumption is sampled. Statistical analysis is performed that assumes the core has node capacitance switching behavior that is approximated by a stationary random process with a Poisson distribution. The statistical analysis determines the number of samples to take during a sample interval. The operational frequency, sample interval, and number of samples are used to determine the number of signals to sample. Signals are chosen that have a high correlation with the node capacitance switching behavior, such as clock enable signals on the last stage of a clock distribution system. Weights with tuned values are assigned to each sampled signal. Sampling occurs during every predetermined number of clock cycles. The weights of asserted sampled signals are summed in order to determine a repeatable power estimation value.

Abstract: A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. Rather than provide a single clock to flip-flop circuits on a semiconductor chip, split clocks are used. A flip-flop receives a master clock signal for a master latch and receives a separate slave clock signal for a slave latch. Master and slave clock gater circuits are coupled to a global clock distribution system and the local flip-flops. The master clock gater circuit receives a delay control signal used to select a delay, wherein the selected delay determines an additional amount of time the master clock signal transitions after the slave clock signal transitions. The use of the delayed master clock on the semiconductor chip may allow a timing path to have more computation time without increasing the clock cycle time. Further, the delay may be chosen to fix timing paths in post-silicon.

Abstract: One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current cycle to provide an interpolated phase for the current cycle. An edge of the interpolated phase for the current cycle has reduced jitter relative to an edge of a corresponding phase of the current cycle. A delay system delays a plurality of other phases of the current cycle to provide delayed other phases, the delayed other phases and the interpolated phase for the current cycle collectively defining a set of adjusted phases for the current cycle.

Abstract: A system and method for soft error recovery (SER) within a flip-flop. A first stage of the flip-flop receives an ungated input clock signal. A second stage of the flip-flop receives a gated input clock signal. The second stage may also store a prebuffered data output and one or more feedback storage values on separate nodes. The flip-flop has SER circuitry used to recover the prebuffered data output and any feedback storage value without requiring a transition of a clock signal.

Abstract: Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic component and a second electronic component connected by one or more serial communication links comprises an offset logic configured to apply a selected offset to signal transmissions to cause a unidirectional delay between the first and the second electronic components to be synchronized for both directions of signal transmissions. A synchronization logic is configured to determine the uni-directional delay for signal transmissions between the first and second electronic components and configured to control the offset logic to apply the selected offset.

Abstract: Systems and methods for error recovery in an integer execution unit of a multi-core processor are disclosed. In an exemplary embodiment a method may comprise checking parity for a transaction in an execution data path having parallel data registers. The method may also comprise copying one of the parallel data registers to a corrupt data register if parity fails.

Abstract: According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Abstract: Devices and methods for managing power on a module are disclosed herein. In one embodiment, a module comprises a first die; a second die; and a power manager. The power manager monitors the power requirements of the first die and the second die and allocates power to the first die and the second die based on the power requirements.