Abstract: In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass filter are connected to first and second inputs respectively of the feedback keeper. The only type of diffusion connected to the first output of the low-pass filter is a P-type diffusion. The only type of diffusion connected to the second output of the low-pass filter is an N-type diffusion. The feedback keeper is connected to an input of the forward inverter.

Abstract: An integrated circuit is provided which in one embodiment includes a first sub-circuit coupled to a first power supply rail providing a first power supply voltage; a second sub-circuit coupled to a second power supply rail providing a second power supply voltage; and first power supply modulation means, coupled to the first sub-circuit, for modulating the first power supply voltage without modulating the second power supply voltage.

Abstract: Systems, methods, and other embodiments associated with a repeatable communication system are disclosed. One example system for receiving signals from an electronic component over a plurality of point-to-point communication links comprises a repeatability logic operably connected to each of the plurality of point-to-point communication links and configured to apply a delay offset to the signals received to compensate for frequency changes in signal transmissions over the plurality of point-to-point communication links.

Abstract: A method of generating a clock signal using a digital frequency synthesizer includes providing a base clock to the digital frequency synthesizer, comparing a phase of an output clock from the digital frequency synthesizer with a phase of a reference signal, and issuing at least one frequency control command to the digital frequency synthesizer to align the phases.

Abstract: A system and method can mitigate voltage fluctuations. According to one embodiment, a delay system provides a delayed version of a first reference signal as a function of a supply voltage. A comparator provides a control signal for controlling a protection device based on the delayed version of the first reference signal and a second reference signal. The amount of delay provided by the delay system defines a threshold based on which the comparator provides the control signal.

Abstract: One disclosed embodiment of the invention is directed to circuit control that comprises sensing a delivered voltage to a portion of an integrated circuit, determining an appropriate frequency for the portion of the integrated circuit, and providing the appropriate frequency to the integrated circuit.

Abstract: Systems and methods are disclosed for providing a temporarily modified output. A waveform control provides a control output that temporarily adjusts to an intermediate level between normal high and low levels during a first operating mode. The waveform control provides the control output to transition periodically between the high and low levels during a second operating mode. A delay network controls the waveform control to provide the output at the intermediate level for a duration during the first operating mode.

Abstract: Systems and methods are provided for generating a current. A first current source generates a first current based on a first current selection signal, and a second current source generates a second current that is a multiple of the first current in response to selection of the first current.

Abstract: A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.

Abstract: The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.

Abstract: A method for calibrating a voltage controlled oscillator (VCO) comprising applying a plurality of known voltages to the input of a VCO, monitoring, for each of the voltages, an output count from the VCO over a set interval, and storing the output counts for each voltage. Also disclosed is a system for calibrating a voltage controlled oscillator (VCO) comprising a plurality of known voltages, wherein the known voltage are connectable to the VCO, and a controller coupled to the output of the VCO, wherein the controller maintains a calibration table of VCO output counts for selected voltage inputs.

Abstract: A memory system includes a first plurality of memory cells, wherein each of the first plurality of memory cells includes a first node and a second node that are configured to have opposite logic values, and a second plurality of memory cells, wherein each of the second plurality of memory cells includes a first node and a second node that are configured to have opposite logic values. Providing a pre-program data value to the first nodes of the first plurality of memory cells, and to the second nodes of the second plurality of memory cells enables the memory system to be pre-programmed.

Abstract: A system and method for measuring integrated circuit processor power demand comprises calibrating one or more voltage controlled oscillators for use as ammeters, calibrating a calibration current source, wherein the calibration current source draws current through a inherent resistance, calibrating the inherent resistance, and interleaving said calibrations in time with calculating the processor power demand using a voltage that is measured across the inherent resistance.

Abstract: Systems and methods are disclosed for controlling an associated circuit. A clock waveform that transitions between normally high and low levels over a cycle in a first operating mode is provided to the associated circuit. The clock waveform is modified to include an intermediate level between the normally high and low levels over a cycle in a second operating mode.

Abstract: According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Abstract: A find-instructions-and-allocate-ports (FIAP) circuit and method are provided for quickly and efficiently locating one or more instructions that are ready for execution during a launch cycle in an out of order processor and allocating one or more ports associated with one or more execution resources to such ready instructions during the launch cycle. In architecture, the processor includes an instruction reordering mechanism, for example, a queue, having a plurality of slots for temporarily storing a plurality of respective instructions. Instructions can be executed in an out of order sequence from the queue. Each slot is provided with the FIAP circuit for causing and preventing launching, when appropriate, of their respective instruction. A plurality of signals is propagated successively through the FIAP circuits of the queue that causes the queue to launch a predefined plurality of the instructions, which corresponds to a predefined plurality of ports associated with the one or more execution resources.

Abstract: One disclosed embodiment of the invention is directed to circuit control that comprises sensing a delivered voltage to a portion of an integrated circuit, determining an appropriate frequency for the portion of the integrated circuit, and providing the appropriate frequency to the integrated circuit.

Abstract: A system and method are disclosed which provide an integrated circuit having a clock signal that is dynamically manipulated in response to detected events within the integrated circuit. In one embodiment, the chip includes event detection circuitry that monitors the operation of the chip and detects events that lead to a power disturbance therein. Circuitry may be included for detecting anticipated operation known to trigger an event, as well as for detecting unanticipated events. Additionally, clock manipulator circuitry is included to manipulate the chip's clock signal responsive detection of an event to enable the chip to cope with such event. In response to an event being detected, the clock manipulator circuitry may dynamically manipulate the clock signal in various manners, such as by altering the clock signal's duty cycle, delaying the occurrence of a transition of the clock signal, or altering the clock signal's frequency, as examples.

Abstract: In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first and second phase comparator, each with at least three inputs and an output are preset to a predetermined logical value by a first control circuit. A first signal is connected to an input of the first and second phase comparators. A second signal is connected to a second input of the second phase comparator and to the input of a programmable dead zone delay circuit. The output of the programmable dead zone delay circuit is connected to a second input of the first phase comparator. A preset value, determined by the first control circuit, is presented on the outputs of the first and second phase comparators. Until metastability is resolved, these outputs retain a valid fail-safe default.

Abstract: A method of operating a static random access memory (SRAM) having a column clear function by performing write operations using a two step process. To perform a write, each cell in a row to be written is preset during a first step. Then, each cell that is to have a zero written to it is cleared using a column clear operation. A column of cells may be cleared by enabling all the rows for clearing, then asserting column clear control signals for each of the columns in the array to be cleared. A subset of columns of a plurality of rows may be cleared by asserting a plurality of column clear signals corresponding to the subset of columns and a plurality of work lines corresponding to the plurality of rows.