Abstract: An embodiment of the invention provides a circuit and method for reducing silent data corruption in storage arrays with no increase in read and write access times. An N bit parity encoder is connected to an N bit storage array. When the N bit array is written, the data used to write into the storage array is also used to generate a parity value by the N bit parity encoder. This parity value is stored in a latch. When the N bit array is read, the current parity value of the parity encoder is presented to the state machine. The state machine compares the current value of the parity encoder to the stored value in the latch. If the parity values, stored and observed, don't match, the state machine indicates that data corruption may have occurred.

Abstract: A method and apparatus for scannable zero-catcher and one-catcher circuits. The catcher circuit of the present invention comprises an input stage. A feedback stage is coupled to the input stage. Scanning logic is coupled to the feedback stage. An output stage is coupled to the feedback stage.

Abstract: The present invention includes a system for and a method of determining noise characteristics of a circuit of an integrated circuit. The circuit is classified based on its topology and measured circuit parameters. Noise characteristics are retrieved using the circuit classification and circuit parameters to calculate a noise response. Classification and characterization may be performed on each individual input.

Abstract: A method of providing critical circuits in a library of circuits, whereby such critical circuits allows designers to apply modifications to them in a controlled manner such that the changes are easy to implement and virtually guaranteed to be correct. The invention comprises a method of performing limited modifications to such critical circuits to alter its characteristics in a controlled manner, and thereafter checking the resulting modified circuit with a circuit simulator for conformance to predetermined specifications that have been assembled for this library critical circuit.

Abstract: Disclosed is an apparatus and method for detecting errors in one-hot words, which have only a single bit set in the absence of errors. The apparatus comprises a plurality of input signal lines, a plurality of switching devices, a plurality of intermediate signal lines, and logic circuitry. The switching devices are connected to the input signal lines. The intermediate signal lines are also connected to the switching devices. The connection is in such a way that when a particular input signal line is set, all intermediate signal lines connected by a switching device to that particular input signal line are forced to a predetermined logic state. The intermediate signal lines are input to the logic circuitry, which outputs a signal indicative of whether at least two of the plurality of input signal lines are set. The method detects non-one-hot conditions in a group of M bits.

Abstract: Current pulse matchers monitor the wires of a static or precharge-pulldown bus. Each current pulse matcher monitors the wire that it is connected to. For a precharge-pulldown bus, if the wire has been discharged during the pulldown cycle of the bus, the precharge current pulse matcher does not consume any current. If, however, the wire was not discharged during the pulldown cycle of the bus, then the precharge current pulse matcher consumes an amount of current that approximates the amount of current used to precharge that wire had it been discharged. For a static bus, the current pulse matcher does not shunt current if the wire has not just made a transition. Otherwise, the static bus current pulse matcher shunts an amount of current that may approximates the amount of current used to transition the bus signal from one logic state to another.

Abstract: Scan chain links which step data through a scan chain using only a single control signal, and which require a reduced number of transistors to scan data into and out of a latch. One scan chain link, which allows the output of a scanned latch to “wiggle”, uses eight transistors and only a single control signal. Another scan chain link, which prevents the output of a scanned latch from “wiggling”, and which allows data to be maintained in a latch during a scan operation if it is so desired, uses twenty-five transistors and two control signals: one control signal for stepping data through a scan chain, and an additional control signal for preventing the output of a scanned latch from wiggling.

Abstract: The present invention provides a precharge circuit that has a first precharged node, a second precharged node, and a latch device. The first precharged node is charged to a high value during a precharge state. In response to a transition from the precharge state to an evaluate state, it either discharges to a low value or remains charged at its high value. The second precharged node has a value in the evaluate state that is based on the value of the first precharged node upon the circuit transitioning to the evaluate state. The latch device is connected to the second precharged node for latching this value in the evaluate state. With the latching device, this value is not affected by the first precharged node once the circuit has sufficiently transitioned to the evaluate state.

Abstract: A method of providing critical circuits in a library of circuits, whereby such critical circuits allows designers to apply modifications to them in a controlled manner such that the changes are easy to implement and virtually guaranteed to be correct. The invention comprises a method of performing limited modifications to such critical circuits to alter its characteristics in a controlled manner, and thereafter checking the resulting modified circuit with a circuit simulator for conformance to predetermined specifications that have been assembled for this library critical circuit.

Abstract: Circuitry for scanning and observing domino CMOS logic or other logic gates. Master and slave stages includes circuitry for latching a bit into the master stage through pulsing of a clock signal and subsequently latching the bit into the slave stage through pulsing of another clock signal. The number of transistors required for scanning is minimized by using existing latch structures within the logic.

Abstract: A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R is greater than W. In such a register file, each register will be accessed by W combined read/write word lines, a single direction line, and R-W read-only word lines. The direction line is asserted during a write operation, and is not asserted during a read operation, and also allows the storage elements comprising each register of the register file to be powered down or enter a high-impedance state during a write operation. During a read operation, the direction line remains deasserted and the storage elements remain powered up and active. For read ports sharing combined read/write word lines with write ports, the direction line is used as a multiplexer signal to enable a read operation at the read port represented by the combined read/write word line.

Abstract: A circuit for limiting loss in a second circuit. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reaches a first predetermined amount of time, where the first predetermined amount of time is related to a parameter of the second circuit. The second timer may produce a second output in the given state if the first timer does not produce the first output in the given state when the duration of the pulse reaches a second predetermined amount of time. The one or more logic gates may have an output that is the same as the pulse unless and until the output of the first timer or the second timer is in the given state, at which time, the output of the one or more logic gates is forced to a non-pulsed state.

Abstract: The present invention includes an apparatus and a method of designing integrated circuits in which the susceptibility of the integrated circuit to noise is estimated by analyzing the components of the circuits. Suspected noise susceptibility factors were investigated to determine the effects of various potential factors on noise characteristics. It was determined that percent of “bad” capacitance to total capacitance of wire coupling pairs of components, the total length of the corresponding wires between pairs of components that are subject to capacitive coupling and driver output impedance of driving circuits each contributed significantly to noise factors in integrated circuits. It was also determined that the integrated circuit being analyzed can be analyzed as pairs of coupled components (drivers, receivers an interconnections between drivers and receivers) to which the noise susceptibility factors can be applied and used to determine the overall susceptibility of noise of the circuit.

Abstract: A system and method are disclosed which utilize an on-chip oscillator to provide the appropriate clock frequency for components of the chip to manage power consumption by the chip. More specifically, in a preferred embodiment of the present invention, an on-chip oscillator is utilized to provide the clock frequency for the chip's core circuitry, and such oscillator can dynamically adjust such clock frequency to manage the chip's power consumption. Thus, such on-chip oscillator generates the processor clock instead of the usual synchronous, externally controlled clock generator. A preferred embodiment of the present invention utilizes a voltage controlled frequency oscillator to control the chip's clock frequency in order to dynamically manage power consumption by the chip. Such oscillator is preferably operable to adjust its output frequency based on the voltage supplied to such oscillator to effectively manage the chip's power consumption.

Abstract: The present invention includes a system for and a method of determining noise characteristics of a circuit of an integrated circuit. The circuit is classified based on its topology and measured circuit parameters. Noise characteristics are retrieved using the circuit classification and circuit parameters to calculate a noise response. Classification and characterization may be performed on each individual input.

Abstract: A system and method which implement a memory component of an integrated circuit as multiple, relatively small sub-arrays of memory to enable great flexibility in organizing memory within the integrated circuit are provided. In a preferred embodiment, the memory component of an integrated circuit is implemented as multiple, relatively small sub-arrays of memory, which enable a designer great flexibility in arranging such sub-arrays within an integrated circuit. Also, in a preferred embodiment, the memory component of an integrated circuit is implemented as multiple memory sub-arrays that are each independent. For example, in a preferred embodiment, each memory sub-array comprises its own decode circuitry for decoding memory addresses that are being requested to be accessed by an instruction, and each memory sub-array comprises its own I/O circuitry.

Abstract: A system and method are disclosed that utilize analog detection of an integrated circuit's (“chip's”) power consumption to enable power consumption management. On-chip circuitry may be utilized to detect analog electrical characteristics of the chip, such as its voltage, from which the chip's power consumption is determined. One embodiment utilizes on-chip circuitry to manage long-term, sustained power consumption of the chip, which encompasses power consumption for approximately a microsecond, as well as more extended time frames. Another embodiment utilizes on-chip circuitry to manage short-term power consumption of the chip, which encompasses power consumption for less than a microsecond (e.g., nanosecond time frame). A preferred embodiment implements both the circuitry for managing long-term power consumption and the circuitry for managing short-term power consumption.

Abstract: The present invention includes an apparatus and a method of designing integrated circuits in which the susceptibility of the integrated circuit to noise is estimated by analyzing the components of the circuits. Suspected noise susceptibility factors were investigated to determine the effects of various potential factors on noise characteristics. It was determined that percent of “bad” capacitance to total capacitance of wire coupling pairs of components, the total length of the corresponding wires between pairs of components that are subject to capacitive coupling and driver output impedance of driving circuits each contributed significantly to noise factors in integrated circuits. It was also determined that the integrated circuit being analyzed can be analyzed as pairs of coupled components (drivers, receivers an interconnections between drivers and receivers) to which the noise susceptibility factors can be applied and used to determine the overall susceptibility of noise of the circuit.

Abstract: Current pulse matchers monitor the wires of a static or precharge-pulldown bus. Each current pulse matcher monitors the wire that it is connected to. For a precharge-pulldown bus, if the wire has been discharged during the pulldown cycle of the bus, the precharge current pulse matcher does not consume any current. If, however, the wire was not discharged during the pulldown cycle of the bus, then the precharge current pulse matcher consumes an amount of current that approximates the amount of current used to precharge that wire had it been discharged. For a static bus, the current pulse matcher does not shunt current if the wire has not just made transition. Otherwise, the static bus current pulse matcher shunts an amount of current that may approximate the amount of current used to transition the bus signal from one logic state to another.

Abstract: An SRAM that has a column clear function with only three vertical lines and six total lines across a cell and a method of operating that cell and an array of those cells. Instead of two bit lines per port and two access devices per port as in a traditional SRAM cell, one bit line and one access device per port is used. In addition, one additional bit line, one additional word line, and two devices in series are used to perform the column clear operation and complete a write operation. The cell is operated by performing write operations using a two step process. To perform a write, each cell in a row to be written is preset during a first step. Then, each cell that is to have a zero written to it is cleared using the additional bit line and additional word line to address the cells to be cleared. A column of cells may be cleared by enabling all the rows for clearing, then asserting column clear control signals for each of the columns in the array to be cleared.