Abstract: A computer-implemented method for remediating disruptions to memory cells is described. In response to detecting a write to an aggressor memory cell, a remediation event detector locates an entry in a data structure based on an identifier of the aggressor memory cell. Based on the located entry, the remediation event detector determines an increment value. The determined increment value is used by the remediation event detector to increment a disturb counter associated with a neighbor memory cell of the aggressor memory cell. When the disturb counter of the neighbor memory cell is greater than or equal to a disturb threshold, a remediator performs selective remediation for the neighbor memory cell.

Abstract: A computer-implemented method for remediating disruptions to memory cells is described. In response to detecting a write to an aggressor memory cell, a remediation event detector locates an entry in a data structure based on an identifier of the aggressor memory cell. Based on the located entry, the remediation event detector determines an increment value. The determined increment value is used by the remediation event detector to increment a disturb counter associated with a neighbor memory cell of the aggressor memory cell. When the disturb counter of the neighbor memory cell is greater than or equal to a disturb threshold, a remediator performs selective remediation for the neighbor memory cell.

Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.

Abstract: Exemplary methods, apparatuses, and systems include a controller that determines that a group of memory cells of a first memory device has an elevated error rate. In response to determining the elevated error rate, the controller identifies a spare group of memory cells. The group of memory cells and the spare group of memory cells span a first dimension and a second dimension that is orthogonal to the first dimension. The controller reads a portion of a logical unit from the group of memory cells along the first dimension of the group. The controller further determines that the group of memory cells and the spare group of memory cells have strong disturb effects in different dimensions and, in response to that determination, writes the portion of the logical unit to the spare group of memory cells along the second dimension of the spare group.

Abstract: Remapping portions of a memory system having a plurality of non-volatile memory dice. A processing device performs a first error analysis of subslice elements to identify a first group of a predetermined number of subslice elements having highest error rates. The processing device determines which of the subslice elements are user subslice elements and remaps user subslice elements of the first group to spare subslice elements to remove subslice elements having the highest rates from a user space of the memory system. The processing device performs a second error analysis to identify a second group of subslice elements having the highest error rates and identifies user subslice elements of the first group that is/are not in the second group. For an identified user subslice element or elements of the first group not in the second group, the processing device reverses the remapping to reinstate removed subslice element(s) back into the user space.

Abstract: Exemplary methods, apparatuses, and systems include a controller detecting a trigger to configure a memory. The memory includes a plurality of dice, including two or more spare dice. The controller accesses each die via one of a plurality of channels. The controller accesses a first spare die via a first channel and the second spare die via a second channel. In response to detecting the trigger, the controller maps a plurality of logical units to the plurality of dice, excluding the two spare dice. The mapping includes mapping each logical unit of the plurality of logical units across multiple dice of the plurality of dice, such that a first half of the plurality of logical units reside on dice accessible via channels other than the first channel and a second half of the plurality of logical units reside on dice accessible via channels other than the second channel.

Abstract: Techniques for remapping portions of an array of non-volatile memory (NVM) resident on a die, in which the die is one of a plurality of NVM dice forming a memory device. A processing device partitions the NVM into a plurality of subslice elements comprising respective physical portions of non-volatile memory having proximal disturb relationships. The NVM has a first portion of the subslice elements allocated as user subslice elements and a second portion as spare subslice elements and the processing device performs an error analysis to identify a predetermined number of subslice elements having highest error rates for a memory domain on the die. For the identified subslice elements having the highest error rates, the processing device remaps user subslice elements to spare subslice elements that were not identified as having the highest error rates to remove subslice element or elements having highest error rates from a user space of the NVM.

Abstract: Techniques for remapping portions of a plurality of non-volatile memory (NVM) dice forming a memory domain. A processing device partitions each NVM die into subslice elements comprising respective physical portions of NVM having proximal disturb relationships. The NVM allocation has user subslice elements and spare subslice elements. For the NVM dice forming the memory domain, the processing device performs an error analysis to identify a predetermined number of subslice elements having highest error rates for the memory domain. Identified user subslice elements having the highest error rates, remap to spare subslice elements of the memory domain that were not identified as having the highest error rates to remove subslice element or elements having highest error rates. At least one user subslice element is remapped from a first die of the memory domain to a second die of the memory domain.

Abstract: A computer-implemented method for remediating disruptions to memory cells is described. The method includes writing user data to an aggressor memory cell and determining a write timestamp and an overwrite count associated with the aggressor memory cell. The write timestamp indicates a last write to the aggressor memory cell and the overwrite count indicates the number of writes to the aggressor memory cell during a time period. Based on the write timestamp and the overwrite count, an increment value is determined for use with a disturb counter associated with a neighbor memory cell of the aggressor memory cell. In particular, the determined increment value is used, in response to the write, to increment the disturb counter associated with the neighbor memory cell. When the disturb counter is greater than or equal to a disturb threshold, remediation for the neighbor memory cell is performed.

Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.

Abstract: A computer-implemented method for writing data to a first media using a set of data structures to reduce potential errors when reading the data from the first media is described. The method includes writing, user data to a set of memory cells in the first media; and storing, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.

Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.

Abstract: A memory device can include three-dimensional memory entities each including a plurality of two-dimensional memory entities. A controller can read data from the memory at a first resolution and collect error rate information from the memory at a second resolution including a portion of a two-dimensional memory entity. The controller can determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information. The controller can determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities.

Abstract: A computer-implemented method for remediating disruptions to memory cells is described. The method includes writing user data to an aggressor memory cell and determining one or more of a write timestamp and an overwrite count associated with the aggressor memory cell. The write timestamp indicates a last write to the aggressor memory cell and the overwrite count indicates the number of writes to the aggressor memory cell during a time period. Based on one or more of the write timestamp and the overwrite count, an increment value is determined for use with a disturb counter associated with a neighbor memory cell of the aggressor memory cell. In particular, the determined increment value is used, in response to the write, to increment the disturb counter associated with the neighbor memory cell. When the disturb counter is greater than or equal to a disturb threshold, remediation for the neighbor memory cell is performed.

Abstract: A memory device having a memory array with a plurality of memory addresses and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each of the d rows corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a first memory address of the plurality of memory addresses and to hash the first memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured to adjust, for each of the d sketch locations, a stored sketch value by a first amount corresponding to the event.

Abstract: A first tier of error correcting code operations on a data block may be performed. The first tier of error correcting code operations on the data block may be determined to be associated with an unsuccessful correction of an error of the data block. Responsive to determining that the first tier of error correcting code operations on the data block are associated with the unsuccessful correction of the error of the data block, a remix operation on the data block to change a logical to physical association of the data block from a first logical association to a second logical association may be performed.

Abstract: A memory device having a memory array and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each row corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a memory address and to hash the memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured, for each of the d sketch locations, to set a detection window flag, if it is not already set, and to adjust a stored sketch value by an amount corresponding to the event. The controller is also configured to evaluate a summary metric corresponding to the stored sketch value in each of the d sketch locations to determine if a threshold value has been reached.

Abstract: A memory device can include three-dimensional memory entities each including a plurality of two-dimensional memory entities. A controller can read data from the memory at a first resolution and collect error rate information from the memory at a second resolution including a portion of a two-dimensional memory entity. The controller can determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information. The controller can determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities.

Abstract: A memory device having a memory array with a plurality of memory addresses and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each of the d rows corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a first memory address of the plurality of memory addresses and to hash the first memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured to adjust, for each of the d sketch locations, a stored sketch value by a first amount corresponding to the event.

Abstract: A memory device having a memory array and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each row corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a memory address and to hash the memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured, for each of the d sketch locations, to set a detection window flag, if it is not already set, and to adjust a stored sketch value by an amount corresponding to the event. The controller is also configured to evaluate a summary metric corresponding to the stored sketch value in each of the d sketch locations to determine if a threshold value has been reached.