Patents by Inventor Samuel E. Bradshaw

Samuel E. Bradshaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11061819
    Abstract: Systems, methods and apparatuses of distributed computing based on Memory as a Service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ameen D. Akel, Samuel E. Bradshaw, Kenneth Marion Curewitz, Sean Stephen Eilert, Dmitri Yudanov
  • Patent number: 11055167
    Abstract: Techniques for remapping portions of a plurality of non-volatile memory (NVM) dice forming a memory domain. A processing device partitions each NVM die into subslice elements comprising respective physical portions of NVM having proximal disturb relationships. The NVM allocation has user subslice elements and spare subslice elements. For the NVM dice forming the memory domain, the processing device performs an error analysis to identify a predetermined number of subslice elements having highest error rates for the memory domain. Identified user subslice elements having the highest error rates, remap to spare subslice elements of the memory domain that were not identified as having the highest error rates to remove subslice element or elements having highest error rates. At least one user subslice element is remapped from a first die of the memory domain to a second die of the memory domain.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: July 6, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Samuel E. Bradshaw, Justin Eno
  • Publication number: 20210202021
    Abstract: Exemplary methods, apparatuses, and systems include a controller to manage memory proximity disturb. The controller identifies a first memory location in response to an access of a second memory location, the first memory location storing a first value. The controller updates a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Jeffrey L. MCVAY, Samuel E. BRADSHAW, Justin ENO
  • Patent number: 11048597
    Abstract: Exemplary methods, apparatuses, and systems include a controller detecting a trigger to configure a memory. The memory includes a plurality of dice, including two or more spare dice. The controller accesses each die via one of a plurality of channels. The controller accesses a first spare die via a first channel and the second spare die via a second channel. In response to detecting the trigger, the controller maps a plurality of logical units to the plurality of dice, excluding the two spare dice. The mapping includes mapping each logical unit of the plurality of logical units across multiple dice of the plurality of dice, such that a first half of the plurality of logical units reside on dice accessible via channels other than the first channel and a second half of the plurality of logical units reside on dice accessible via channels other than the second channel.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 29, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Justin Eno, Samuel E. Bradshaw
  • Patent number: 11048580
    Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: June 29, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Samuel E. Bradshaw, Justin Eno, Sean Stephen Eilert, Sai Krishna Mylavarapu
  • Publication number: 20210191875
    Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.
    Type: Application
    Filed: March 4, 2021
    Publication date: June 24, 2021
    Inventors: Samuel E. Bradshaw, Shivasankar Gunasekaran, Hongyu Wang, Justin M. Eno
  • Patent number: 11036593
    Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Samuel E. Bradshaw, Justin M. Eno
  • Publication number: 20210157646
    Abstract: Enhancement or reduction of page migration can include operations that include scoring, in a computing device, each executable of at least a first group and a second group of executables in the computing device. The executables can be related to user interface elements of applications and associated with pages of memory in the computing device. For each executable, the scoring can be based at least partly on an amount of user interface elements using the executable. The first group can be located at first pages of the memory, and the second group can be located at second pages. When the scoring of the executables in the first group is higher than the scoring of the executables in the second group, the operations can include allocating or migrating the first pages to a first type of memory, and allocating or migrating the second pages to a second type of memory.
    Type: Application
    Filed: November 25, 2019
    Publication date: May 27, 2021
    Inventors: Dmitri Yudanov, Samuel E. Bradshaw
  • Publication number: 20210157718
    Abstract: Reduction of page migration while maintaining benefits of migration can include operations that include scoring objects and executables of application processes of a computing device based on placement and movement of the objects and executables in memory of the device, as well as grouping the objects and executables based on the placement and movement of the objects and executables in the memory. The operations can also include controlling loading and storing, in a first type of memory of the memory, at a first plurality of pages of the memory, a first group of the objects and executables at least according to the scoring. And, the operations can include controlling loading and storing, in at least one additional type of memory of the memory, at one or more additional pluralities of pages of the memory, at least one additional group of the objects and executables at least according to the scoring.
    Type: Application
    Filed: November 25, 2019
    Publication date: May 27, 2021
    Inventors: Dmitri Yudanov, Samuel E. Bradshaw
  • Publication number: 20210149595
    Abstract: A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory subsystem can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Shivasankar Gunasekaran, Samuel E. Bradshaw, Justin M. Eno, Ameen D. Akel
  • Publication number: 20210132690
    Abstract: An apparatus having a computing device and a user interface—such as a user interface having a display that can provide a graphical user interface (GUI). The apparatus also includes a camera, and a processor in the computing device. The camera can be connected to the computing device and/or the user interface, and the camera can be configured to capture pupil location and/or eye movement of a user. The processor can be configured to: identify a visual focal point of the user relative to the user interface based on the captured pupil location, and/or identify a type of eye movement of the user (such as a saccade) based on the captured eye movement. The processor can also be configured to control parameters of the user interface based at least partially on the identified visual focal point and/or the identified type of eye movement.
    Type: Application
    Filed: November 5, 2019
    Publication date: May 6, 2021
    Inventors: Dmitri Yudanov, Samuel E. Bradshaw
  • Publication number: 20210132689
    Abstract: An apparatus having a wearable structure, a computing device, a display, and a camera. The wearable structure is configured to be worn by a user and can be connected to the computing device, the display, and/or the camera. The computing device can be connected to the wearable structure, the display, and/or the camera. The display can be connected to the wearable structure, the computing device, and/or the camera. The display is configured to provide a graphical user interface (GUI). The camera can be connected to the computing device, the wearable structure, and/or the display. The camera is configured to capture eye movement of the user. A processor in the computing device is configured to identify one or more eye gestures from the captured eye movement. And, the processor is configured to control one or more parameters of the display and/or the GUI based on the identified eye gesture(s).
    Type: Application
    Filed: November 5, 2019
    Publication date: May 6, 2021
    Inventors: Dmitri Yudanov, Samuel E. Bradshaw
  • Publication number: 20210103463
    Abstract: Customized root processes for groups of applications in a computing device. A computing device (e.g., a mobile device) can monitor usage of applications. The device can then store data related to the usage of the applications, and group the applications into groups according to the stored data. The device can customize and execute a root process for a group of applications according to usage common to each application in the group. The device can generate patterns of prior executions shared amongst the applications in the group based on the stored data common to each application in the group, and execute the root process of the group according to the patterns. The device can receive a request to start an application from the group from a user of the device, and start the application upon receiving the request and by using the root process of the group of applications.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 8, 2021
    Inventors: Dmitri Yudanov, Samuel E. Bradshaw
  • Publication number: 20210103446
    Abstract: In a mobile device, processes of an application can be monitored and scored for initial data distribution. Specifically, a method can include monitoring processes of an application, and scoring objects or components used by the processes to determine placement of the objects or components in memory during initiation of the application. The method can also include, during initiation of the application, loading, into a first portion of the memory, at least partially, the objects or components scored at a first level. The method can also include, during initiation of the application, loading, into a second portion of the memory, at least partially, the objects or components scored at a second level. The objects or components scored at the second level can be less critical to the application than the objects or components scored at the first level.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 8, 2021
    Inventors: Dmitri Yudanov, Samuel E. Bradshaw
  • Publication number: 20210103462
    Abstract: A computing device (e.g., a mobile device) can execute a root process of an application to an initial point according to patterns of prior executions of the application. The root process can be one of many respective customized root processes of individual applications in the computing device. The device can receive a request to start the application from a user of the device. And, the device can start the application upon receiving the request to start the application and by using the root process of the application. At least one of the executing, receiving, or starting can be performed by an operating system in the device. The device can also fork the root process of the application into multiple processes, and can start upon receiving the request to start the application and by using at least one of the multiple processes according to the request to start the application.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 8, 2021
    Inventors: Dmitri Yudanov, Samuel E. Bradshaw
  • Patent number: 10963396
    Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Samuel E. Bradshaw, Shivasankar Gunasekaran, Hongyu Wang, Justin M. Eno
  • Publication number: 20210081121
    Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Kenneth Marion Curewitz, Shivasankar Gunasekaran, Ameen D. Akel, Hongyu Wang, Justin M. Eno, Shivam Swami, Samuel E. Bradshaw
  • Publication number: 20210081324
    Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Samuel E. Bradshaw, Justin M. Eno, Sean S. Eilert, Shivasankar Gunasekaran, Hongyu Wang, Shivam Swami
  • Publication number: 20210081326
    Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Kenneth Marion Curewitz, Sean S. Eilert, Hongyu Wang, Samuel E. Bradshaw, Shivasankar Gunasekaran, Justin M. Eno, Shivam Swami
  • Publication number: 20210081141
    Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Kenneth Marion Curewitz, Shivam Swami, Samuel E. Bradshaw, Justin M. Eno, Ameen D. Akel, Sean S. Eilert