Patents by Inventor Samuel J. Anderson

Samuel J. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11944130
    Abstract: A vaporizer device includes various modular components. The vaporizer device includes a first subassembly. The first subassembly includes a cartridge connector that secures a vaporizer cartridge to the vaporizer device and includes at least two receptacle contacts that electrically communicate with the vaporizer cartridge. The vaporizer device includes a second subassembly. The second subassembly includes a skeleton defining a rigid tray that retains at least a power source. The vaporizer device also includes a third subassembly. The third subassembly includes a plurality of charging contacts that supply power to the power source, and an end cap that encloses an end of the vaporizer device.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: April 2, 2024
    Assignee: JUUL Labs, Inc.
    Inventors: Samuel C. Anderson, Wei-Ling Chang, Brandon Cheung, Steven Christensen, Joseph Chun, Joseph R. Fisher, Jr., Nicholas J. Hatton, Kevin Lomeli, James Monsees, Andrew L. Murphy, Claire O'Malley, John R. Pelochino, Hugh Pham, Vipul V. Rahane, Matthew J. Taschner, Val Valentine, Kenneth Wong
  • Publication number: 20240085949
    Abstract: An apparatus can include a display, a facial interface, and a connector between the display and the facial interface. The facial interface can at least translate or rotate relative to the display via the connector.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 14, 2024
    Inventors: Darshan R. Kasar, Samuel G. Smith, Jonathan M. Anderson, Erin M. Bosch, Muhammad F. Hossain, Liam R. Martinez, Andrew Gallaher, Ian A. Guy, Brian Baillargeon, Keith W. Kirkwood, Timothy J. Rasmussen
  • Publication number: 20230207568
    Abstract: A power transistor has a plurality of cells, each cell having a notch formed in a substrate. An insulating material, such as an oxide, is formed within the notch. A semiconductor layer is formed over the substrate and insulating material. The semiconductor layer has a first type of semiconductor material and a second type of semiconductor material opposite the first type of semiconductor material to form the power transistor. A width of the insulating material within the notch is less than a width of the semiconductor layer so that a portion of the substrate extends to the semiconductor layer. The notch can have a slope or a step. The insulating material has a first thickness and a second thickness greater than the first thickness within the notch. The insulating material may extend completely across the interface between substrate and semiconductor layer, or only partially across the interface.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 29, 2023
    Applicant: IceMos Technology Limited
    Inventors: Takeshi Ishiguro, Samuel J. Anderson, Aymeric Privat
  • Patent number: 11687445
    Abstract: A device, method and system is directed to fast data storage on a block storage device. New data is linearly written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is linearly written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: June 27, 2023
    Inventors: Douglas Dumitru, Samuel J. Anderson
  • Publication number: 20230154977
    Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. An insulating material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A first insulating layer is formed between the insulating material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region. A conductive layer is formed over the semiconductor layer. The source region is coupled to the conductive layer.
    Type: Application
    Filed: October 7, 2022
    Publication date: May 18, 2023
    Applicant: IceMos Technology Limited
    Inventors: Takeshi Ishiguro, Aymeric Privat, Samuel J. Anderson
  • Publication number: 20230154976
    Abstract: A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. A polysilicon material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A conductive layer is formed over the semiconductor layer. The polysilicon material is coupled to the conductive layer and operates as a field plate. A first insulating layer is formed between the polysilicon material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region.
    Type: Application
    Filed: October 7, 2022
    Publication date: May 18, 2023
    Applicant: IceMos Technology Limited
    Inventors: Takeshi Ishiguro, Aymeric Privat, Samuel J. Anderson
  • Publication number: 20230061775
    Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third semiconductor layer made of the second semiconductor material can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device or electrical component is formed in the second semiconductor layer. The electrical component can be a power MOSFET. A first insulating layer, such as an oxide layer, is formed over the electrical component, and second insulating layer, such as a nitride layer, is formed over the first insulating layer for protection against radiation.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 2, 2023
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Publication number: 20230067511
    Abstract: A semiconductor device has a substrate. The substrate can be multiple layers. A first semiconductor layer made of a first semiconductor material is disposed over the substrate. The first semiconductor material can be substantially defect-free silicon carbide. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third layer can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 2, 2023
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Publication number: 20230064236
    Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The first semiconductor material is substantially defect-free silicon carbide, and the second semiconductor material is silicon. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 2, 2023
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Publication number: 20230061047
    Abstract: A semiconductor device has a first substrate made of a first semiconductor material, such as silicon. A sacrificial layer is formed over a first surface of the first substrate. A seed layer is formed over the sacrificial layer. A compliant layer is formed over a second surface of the first substrate opposite the first surface of the first substrate. A first semiconductor layer made of a second semiconductor material, such as silicon carbide, dissimilar from the first semiconductor material is formed over the sacrificial layer. The first substrate and sacrificial layer are removed leaving the first semiconductor layer substantially defect-free. The first semiconductor layer containing the second semiconductor material is formed at a temperature greater than a melting point of the first semiconductor material. A second semiconductor layer is formed over the first semiconductor layer with an electrical component formed in the second semiconductor layer.
    Type: Application
    Filed: July 11, 2022
    Publication date: March 2, 2023
    Applicant: IceMos Technology Limited
    Inventors: Aymeric Privat, Takeshi Ishiguro, Cathal Duffy, Samuel J. Anderson
  • Publication number: 20230060866
    Abstract: A semiconductor device has a first substrate and a first semiconductor layer having a first semiconductor material formed over the first substrate. A surface of the first semiconductor layer has a first element of the first semiconductor material. A first surface of a second semiconductor layer having the first semiconductor material is joined to the surface of the first semiconductor layer. The first surface of the second semiconductor layer has a second element of the first semiconductor material different from the first element. The first semiconductor material is silicon carbide or cubic silicon carbide. The first element is silicon or carbon, and the second element is carbon or silicon. The semiconductor device provides characteristics of radiation hardening. A third semiconductor layer is formed over a second surface of the second semiconductor layer opposite the first surface. An electrical component is formed over the second semiconductor layer.
    Type: Application
    Filed: August 24, 2022
    Publication date: March 2, 2023
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Publication number: 20230065348
    Abstract: A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third semiconductor layer made of the second semiconductor material can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 2, 2023
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Takeshi Ishiguro, Cathal Duffy, Aymeric Privat
  • Patent number: 11545565
    Abstract: A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: January 3, 2023
    Inventor: Samuel J. Anderson
  • Patent number: 11455099
    Abstract: A device, memory, method and system directed to fast data storage on a block storage device that reduces operational wear on the device. New data is written to an empty write block with a number of write blocks being reused. A location of the new data is tracked. Metadata associated with the new data is written. A lookup table may be updated based in part on the metadata. The new data may be read based the lookup table configured to map a logical address to a physical address.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: September 27, 2022
    Inventors: Douglas Dumitru, Samuel J. Anderson
  • Publication number: 20220236261
    Abstract: An atomic level deposition for mass functionalization of a cavity filled with a pathogen sensitive antibody reagent to functionalize each Biosensor using atomic level vapor phase deposition enables high volume production of this sensor technology. A biosensor has a first substrate and a second substrate with a cavity formed in the first substrate to form a membrane. Holes is formed through the second substrate. An aluminum oxide layer is formed over the cavity and into the holes to form cores. The cavity is filled with a pathogen sensitive antibody reagent. A biofluid sample with the pathogen is deposited over the membrane. The biofluid is drawn through the cores to mix with the antibody reagent. The antibodies combine with the pathogen to change the impedance along the current path. The presence of the pathogen changes the ionic current flow through the biosensor for a positive detection of the pathogen.
    Type: Application
    Filed: January 26, 2021
    Publication date: July 28, 2022
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Hugh J. Griffin
  • Publication number: 20220236214
    Abstract: An atomic level deposition for mass functionalization of a cavity filled with a pathogen sensitive antibody reagent to functionalize each biosensor using atomic level vapor phase deposition enables high volume production of this sensor technology. A biosensor has a first substrate and a second substrate with a cavity formed in the first substrate to form a membrane. Holes are formed through the second substrate. An aluminum oxide layer is formed over the cavity and into the holes to form cores. The cavity is filled with a pathogen sensitive antibody reagent. A biofluid sample with the pathogen is deposited over the membrane. The biofluid is drawn through the cores to mix with the antibody reagent. The antibodies combine with the pathogen to change the impedance along the current path. The presence of the pathogen changes the ionic current flow through the biosensor for a positive detection of the pathogen.
    Type: Application
    Filed: February 9, 2021
    Publication date: July 28, 2022
    Applicant: IceMos Technology Limited
    Inventors: Samuel J. Anderson, Hugh J. Griffin
  • Publication number: 20220123134
    Abstract: A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Applicant: IceMos Technology Limited
    Inventor: Samuel J. Anderson
  • Publication number: 20210287149
    Abstract: Systems, methods, and devices for accessing and visualizing supply chain data. A computing system can receive an indication of a selected facility item. The selected facility item can represent a particular supply chain item that is processed at a particular facility of a set of facilities in an organization. The system can render a first view of a user interface pertaining to the selected facility item. The computing system can receive a selection of a first user interface element within the first view of the user interface, and in response, transition from the first view of the user interface that includes the item flow map to a second view of the user interface that shows additional information pertaining to the selected facility item or the particular facility represented by the selected facility item that is not shown in the first view.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Viruru Phaniraj, Karl W. Bloedorn, Samuel J. Anderson, Michael J. Lovell, Peter A. Hockey, Jennifer L. Austin, Jeffrey L. Ranch, Andrew J. Pung, David C. Borchard, Donald S.D. Hart, II, Jim D. Jacob, Kirk R. Soule, Matthew J. Siemer, Scott R. Jilek
  • Publication number: 20210287161
    Abstract: A computing system may receive an indication of a selected facility item that represents a particular supply chain item processed at a particular facility, render, for display, a first view of a user interface pertaining to the selected facility item, that includes an item flow map that shows a flow of the particular supply chain item represented by the selected facility item between at least two facilities, receive a selection of a user interface element shown within the first view of the user interface; and in response to receipt of the selection of the user interface element, render, for display on the screen, a second view of the user interface that shows additional information pertaining to the selected facility item or the particular facility represented by the selected facility item, where the additional information is not shown in the first view of the user interface.
    Type: Application
    Filed: March 10, 2021
    Publication date: September 16, 2021
    Inventors: Viruru Phaniraj, Karl W. Bloedorn, Samuel J. Anderson, Michael J. Lovell, Peter H. Hockey, Jennifer L. Austin, Jeffrey L. Ranch, Andrew J. Pung, David C. Borchard, Donald S.D. Hart, II, Jim D. Jacob, Kirk R. Soule, Matthew J. Siemer, Scott R. Jilek
  • Patent number: 10860255
    Abstract: A system, method and apparatus directed to fast data storage on a block storage device. New data is written to an empty write block. If the new data is compressible, a compressed version of the new is written into the meta data. A location of the new data is tracked. Meta data associated with the new data is written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address. Disk operations may use state data associated with the meta data to determine the empty write block. A write speed-limit may also be determined based on a lifetime period, a number of life cycles and a device-erase-sector-count for the device. A write speed for the device may be slowed based on the determined write speed-limit.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 8, 2020
    Inventors: Douglas Dumitru, Samuel J. Anderson