Abstract: A power MOSFET is provided on a semiconductor die to withstand radiation exposure. The semiconductor die is mounted on a die flag of a leadframe. The MOSFET includes a substrate and epitaxial layer formed over the substrate. A source region is formed in a surface of the semiconductor die. The source region is coupled to the die flag. A contact pad is formed on the source region. A base region is formed in the surface of the semiconductor die adjacent to the source region. The base region is electrically connected to the contact pad. A drain region is formed in the surface of the semiconductor die. The drain region is coupled to a first wire bond pad on the leadframe. A gate structure is formed over a channel between the source region and drain region. The gate structure is coupled to a second wire bond pad on the leadframe.

Abstract: A lateral power semiconductor device has a substrate and an isolation layer formed over the substrate for reducing minority carrier storage in the substrate. A well region is formed over the isolation layer. A source region, drain region, and channel region are formed in the well. A first region is formed on a surface of the lateral power semiconductor device adjacent to the source region. The lateral power semiconductor device has a body diode between the first region and drain region. The isolation layer confines the minority carrier charge from the body diode to a depth of less than 20 ?m from the surface of the lateral power semiconductor device. In one embodiment, the isolation layer is a buried oxide layer and the substrate is an n-type or p-type handle wafer. Alternatively, the isolation layer is an epitaxial layer and the substrate is made with N+ or P+ semiconductor material.

Abstract: There is provided herein exemplary embodiments of a semiconductor device constructed in accordance with the present invention. The device comprises: a semiconductor chip having a lateral power transistor device formed therein. The chip has an upper surface and source, drain and gate contact terminals on the upper surface thereof. Each of the source, drain and gate contact terminals have a conductive ball or pillar bump thereon. A metal lead frame spans the upper surface of the chip, the metal lead frame being in electrical contact with the conductive balls or pillar bumps. A capsule encases the chip and at least a portion of the metal lead frame such that opposite ends of the metal lead frame protrudes from opposite sides of the capsule.

Abstract: A method of fabricating a multi-chip package including an aluminum silicon substrate with an aluminum nitride layer thereon forming an electrically insulated surface and aluminum heat conductive areas positioned on the insulated surface. Conductors on the surface of the substrate defining mounting areas and external connections with each mounting area positioned adjacent an associated one of the heat conductive areas and a semiconductor chip mounted in each mounting area. Heat conductive elements connected to the rear surface of each chip and to the associated one of the plurality of heat conductive areas, and each chip encapsulated with reworkable encapsulant.

Abstract: An optical isolator (10) includes an opto-electronic emitter (16) and an opto-electronic detector (17) mounted over offset portions (12, 13) of a leadframe (11). The offset portions (12, 13) form angles (14, 15) with other portions (24, 25) of the leadframe (11). An optically transmissive material (22) encapsulates the opto-electronic emitter (16) and the opto-electronic detector (17), and a reflective material (20) is located above the opto-electronic emitter (16) and the opto-electronic detector (17). An optically insulative packaging material (26) encapsulates the optically transmissive material (22).

Abstract: An optical pressure sensor (10) uses a holographic link (41) to couple light (17) from an optical interferometer (40) to a pressure sensing element (13), and to couple return light (18) back to an optical interferometer (40). The optical link (41) uses holographic reflectors (24, 26, 27, 28, 29, and 31) to guide the light (17, 18) through the optical link (41).

Abstract: A liquid cooled power dissipation apparatus (10) includes a metal matrix composite heat sink (11) with an insulation layer (17) integral to the apparatus (10). The insulation layer (17) is made integral to the apparatus (10) during infiltration of the metal matrix composite heat sink (11). Electronic components 23 are situated on top of the insulation layer (17).

Abstract: A wirebondless module package and method of fabrication including a molded preform of porous SiC with a cavity having therein an AlN substrate defining a plurality of pockets. The preform being infiltrated with Al and the Al being deposited in each of the pockets. A semiconductor die mounted on the Al in one of the pockets. A dielectric layer covering the Al and defining openings therethrough positioned to expose the aluminum and a connection to the die. A conductive material positioned on the dielectric layer in contact with the die and the Al so as to define terminals and interconnections between the die and the terminals.

Abstract: An encapsulated microelectronic device (100) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three-fourths of a millimeter and has a bottom metallization consisting of aluminum (407)/chromium (405)/nickel (403)/gold (401). The semiconductor device (305) has a contact (115) attached to the top. The encapsulated microelectronic device (100) has a molded top (120) surrounding the semiconductor device (305). The molded top (120) is made from low stress molding material.

Abstract: An encapsulated microelectronic device (100 ) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three-fourths of a millimeter and has a bottom metallization consisting of aluminum (407)/chromium (405)/nickel (403)/gold (401). The semiconductor device (305) has a contact (115) attached to the top. The encapsulated microelectronic device (100) has a molded top (120) surrounding the semiconductor device (305 ). The molded top (120) is made from low stress molding material.

Abstract: A method for forming a power circuit package (45) having a porous base structure (20) electrically isolated from a first porous die mount (21) and a second porous die mount (22) by a dielectric material (29). The porous base structure (20) is bonded to a second surface of the the dielectric material (29) whereas the first porous die mount (21), and the second porous die mount (22) are bonded to a first surface of the dielectric material (29). Simultaneous with the bonding step, the porous base structure (20), the first porous die mount (21), and the second porous die mount (22) are impregnated with a conductive material. Semiconductor die (32, 33, 34, and 35) are bonded to the impregnated die mounts. The semiconductor die (32, 33, 34, and 35) are then encapsulated by a molding compound.

Abstract: A method of forming an insulated gate semiconductor device (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: A method of forming an insulated gate semiconductor device (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: An encapsulated microelectronic device (100) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three-fourths of a millimeter and has a bottom metallization consisting of aluminum (407)/chromium (405)/nickel (403)/gold (401). The semiconductor device (305) has a contact (115) attached to the top. The encapsulated microelectronic device (100) has a molded top (120) surrounding the semiconductor device (305). The molded top (120) is made from low stress molding material.

Abstract: A method for forming a power circuit package (45) having a porous base structure (20) electrically isolated from a first porous die mount (21) and a second porous die mount (22) by a dielectric material (29). The porous base structure (20) is bonded to a second surface of the the dielectric material (29) whereas the first porous die mount (21 ) , and the second porous die mount (22 ) are bonded to a first surface of the dielectric material (29). Simultaneous with the bonding step, the porous base structure (20) , the first porous die mount (21) , and the second porous die mount (22) are impregnated with a conductive material. Semiconductor die (32, 33, 34, and 35) are bonded to the impregnated die mounts. The semiconductor die (32, 33, 34, and 35) are then encapsulated by a molding compound.

Abstract: An improved damper diode is obtained by replacing the usual step junction (P.sup.+ -Nu-N.sup.+) structure of the prior art with an epitaxial double sided Pi-Nu structure (i.e., P.sup.+ -Pi-Nu-N.sup.+) in which the thickness and impurity concentrations of the Pi and Nu regions are substantially equal and have a combined thickness about equal to the prior art Nu region for the same voltage. Improved transient response (TFR), better transient energy absorption capability (UIS) and lower forward transient turn-on peak over-shoot voltage (TOPO) is obtained for the same or higher reverse breakdown voltage (BVR), in the same or smaller die size.

Abstract: A bracket for mounting the head rail of a venetian blind to a support surface of a window opening. The head rail is in the form of channel member of U-shaped cross section comprising a base member pivotally mounted to a support surface, a pair of flexible, resilient legs depending from the base member having tangs at their terminal ends engageable with locking beads running the length of the head rail channel and rotatable to a position wherein the tangs release the channel member.

Abstract: A mounting bracket which is simple, economic to manufacture and easy to install for the detachable mounting the head rail of a venetian blind assembly in a window opening or the like. In one form the bracket is of box-like configuration having panels with means for securing it to the side, top or front support surface of the window frame, a hinged front panel permitting pivoting from an open position to receive the ends of the head rail and locking means for latching the front panel in a closed position with the head rail in place. In another form, the bracket has flexible legs with tangs to engage with longitudinal ribs in the head rail and is pivotally mounted to release from the head rail when desired. Other features include a bumper insert for the head rail to resist transverse displacement when raising and lowering the blind and a novel control rod and ladder string arrangement facilitating complete closing of all the slats.