Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Abstract: Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.

Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.

Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.

Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.