Patents by Inventor Sandeep B Sane

Sandeep B Sane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11983135
    Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Anshuman Thakur, Md Altaf Hossain, Mahesh Kumashikar, Kemal Aygün, Casey Thielen, Daniel Klowden, Sandeep B. Sane
  • Publication number: 20240145395
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Patent number: 11901299
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala
  • Patent number: 11824013
    Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: November 21, 2023
    Assignee: Intel Corporation
    Inventors: Lauren A. Link, Andrew J. Brown, Sheng C. Li, Sandeep B. Sane
  • Publication number: 20230107106
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20230085944
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core, where the core comprises an organic material. In an embodiment, a via is provided through a thickness of the core. In an embodiment, a shell is around the via, where the shell comprises a magnetic material. In an embodiment, a mold layer is over the core, and a bridge is embedded in the mold layer. In an embodiment, a column is through the mold layer, where the column is aligned with the via.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Bai NIE, Brandon C. MARIN, Sandeep B. SANE, Leonel ARANA, Srinivas V. PIETAMBARAM, Tarek A. IBRAHIM
  • Patent number: 11557541
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala
  • Patent number: 11417592
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nachiket R. Raravikar, Sandeep B. Sane
  • Publication number: 20220100692
    Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Dheeraj SUBBAREDDY, Ankireddy NALAMALPU, Anshuman THAKUR, MD Altaf HOSSAIN, Mahesh KUMASHIKAR, Kemal AYGÜN, Casey THIELEN, Daniel KLOWDEN, Sandeep B. SANE
  • Patent number: 11276625
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Siddarth Kumar, Shubhada H. Sahasrabudhe, Sandeep B. Sane, Shalabh Tandon
  • Publication number: 20210287974
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.
    Type: Application
    Filed: September 29, 2016
    Publication date: September 16, 2021
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, Nachiket R. Raravikar, Sandeep B. Sane
  • Publication number: 20210280495
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.
    Type: Application
    Filed: September 29, 2016
    Publication date: September 9, 2021
    Applicant: Intel Corporation
    Inventors: Siddarth Kumar, Shubhada H. Sahasrabudhe, Sandeep B. Sane, Shalabh Tandon
  • Publication number: 20210050306
    Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 18, 2021
    Applicant: INTEL CORPORATION
    Inventors: Lauren A. Link, Andrew J. Brown, Sheng C. Li, Sandeep B. Sane
  • Patent number: 10811366
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20190279960
    Abstract: Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.
    Type: Application
    Filed: December 14, 2016
    Publication date: September 12, 2019
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, Edvin Cetegen, Sandeep B. Sane
  • Patent number: 10325860
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Publication number: 20190148311
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Patent number: 9953934
    Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Siddarth Kumar, Sandeep B Sane, Shubhada H. Sahasrabudhe, Shalabh Tandon
  • Publication number: 20170309578
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 26, 2017
    Applicant: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane