Patents by Inventor Sandeep B Sane

Sandeep B Sane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210050306
    Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 18, 2021
    Applicant: INTEL CORPORATION
    Inventors: Lauren A. Link, Andrew J. Brown, Sheng C. Li, Sandeep B. Sane
  • Patent number: 10811366
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20190279960
    Abstract: Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.
    Type: Application
    Filed: December 14, 2016
    Publication date: September 12, 2019
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, Edvin Cetegen, Sandeep B. Sane
  • Patent number: 10325860
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Publication number: 20190148311
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Patent number: 9953934
    Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Siddarth Kumar, Sandeep B Sane, Shubhada H. Sahasrabudhe, Shalabh Tandon
  • Publication number: 20170309578
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 26, 2017
    Applicant: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Publication number: 20170178987
    Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventors: Siddarth Kumar, Sandeep B. Sane, Shubhada H. Sahasrabudhe, Shalabh Tandon
  • Patent number: 9659899
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Sandeep B. Sane, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Patent number: 9659908
    Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Shubhada H. Sahasrabudhe, Sandeep B Sane, Siddarth Kumar, Shalabh Tandon
  • Publication number: 20170133350
    Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: Shubhada H. Sahasrabudhe, Sandeep B. Sane, Siddarth Kumar, Shalabh Tandon
  • Publication number: 20170032991
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 2, 2017
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Patent number: 9394619
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Mukul P. Renavikar, Sandeep B. Sane
  • Publication number: 20160172222
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Patent number: 9368461
    Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: June 14, 2016
    Assignee: INTEL CORPORATION
    Inventors: Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe, Sandeep B. Sane
  • Patent number: 9299672
    Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 29, 2016
    Assignee: INTEL CORPORATION
    Inventors: Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe, Sandeep B. Sane
  • Publication number: 20150333022
    Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 19, 2015
    Inventors: Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe, Sandeep B. Sane
  • Publication number: 20150318258
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.
    Type: Application
    Filed: July 10, 2015
    Publication date: November 5, 2015
    Applicant: INTEL CORPORATION
    Inventors: SANDEEP B. SANE, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Patent number: 9123732
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Sandeep B. Sane, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon