Patents by Inventor Sandeep B Sane

Sandeep B Sane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090275175
    Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.
    Type: Application
    Filed: July 13, 2009
    Publication date: November 5, 2009
    Inventors: Sandeep B. Sane, Biju Chandran
  • Patent number: 7579213
    Abstract: A process for assembling a package for a semiconductor device is described. The process includes reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventors: Sandeep B Sane, Biju Chandran
  • Patent number: 7312527
    Abstract: A method, apparatus and system with a semiconductor package including a thermal interface material dam enclosing a volume of thermal interface material.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Sandeep B. Sane, Nitin Deshpande, Chia-Pin Chiu
  • Patent number: 7304391
    Abstract: A method of packaging a die includes reflowing the solder to electrically connect the die to a substrate at a first temperature, cooling the die and substrate to a second temperature, and placing a heated epoxy in contact with the die and the substrate. The method also includes holding the die and substrate at the second temperature for a time sufficient to allow the epoxy to cure, and cooling the die, substrate and epoxy. The second temperature is less than the first temperature. In addition, the die and substrate are not cooled to a temperature significantly below the second temperature until after the heated epoxy is placed in contact with the die and substrate.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: December 4, 2007
    Assignee: Intel Corporation
    Inventors: Sandeep B Sane, Biju Chandran
  • Patent number: 7166540
    Abstract: A method and apparatus for mounting semiconductor die and integral heat spreader are disclosed. In one embodiment, thermal expansion of the integral heat spreader is restricted by physical constraints during the process of heating interface material that bonds the integral heat spreader and semiconductor die together. In an alternative embodiment, thermal expansion of the integral hat spreader is restricted by applying an external compressive force to the integral heat spreader while heating interface material that bonds the integral heat spreader and semiconductor die together.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: January 23, 2007
    Assignee: Intel Corporation
    Inventors: Nitin A. Deshpande, Sandeep B. Sane
  • Patent number: 6919224
    Abstract: A method of packaging a die includes reflowing the solder to electrically connect the die to a substrate at a first temperature, cooling the die and substrate to a second temperature, and placing a heated epoxy in contact with the die and the substrate. The method also includes holding the die and substrate at the second temperature for a time sufficient to allow the epoxy to cure, and cooling the die, substrate and epoxy. The second temperature is less than the first temperature. In addition, the die and substrate are not cooled to a temperature significantly below the second temperature until after the heated epoxy is placed in contact with the die and substrate.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 19, 2005
    Assignee: Intel Corporation
    Inventors: Sandeep B Sane, Biju Chandran
  • Patent number: 6788859
    Abstract: A method and an article made by a method for embedding optical fibers into an organic laminate structure. The optical fiber cabling, along with its cladding, is placed upon a first laminate layer that includes a composite made of silica fillers and a frictionless material such as polytetrafluoroethylene (PTFE). Then a second layer of PTFE material with silica fillers and copper sheeting is placed on top of the PTFE with silica fillers composite. The PTFE material with silica fillers flows about the optical fibers at a temperature approximately fifty degrees above the PTFE with silica fillers material's melting point. This procedure completely encases the optical fibers within an opaque sheath.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: September 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Voya R. Markovich, Sandeep B. Sane, Sanjeev Sathe