Patents by Inventor Sandeep B Sane

Sandeep B Sane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150318258
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.
    Type: Application
    Filed: July 10, 2015
    Publication date: November 5, 2015
    Applicant: INTEL CORPORATION
    Inventors: SANDEEP B. SANE, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Patent number: 9123732
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Sandeep B. Sane, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Publication number: 20150187622
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2013
    Publication date: July 2, 2015
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Patent number: 8941236
    Abstract: Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: January 27, 2015
    Assignee: Intel Corporation
    Inventors: Ameya Limaye, Richard J. Harries, Sandeep B. Sane
  • Publication number: 20140268534
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Inventors: Rajen S. Sidhu, Mukul P. Renavikar, Sandeep B. Sane
  • Publication number: 20140091470
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Sandeep B. Sane, Shandar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Publication number: 20140091456
    Abstract: Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Ameya LIMAYE, Richard J. HARRIES, Sandeep B. SANE
  • Patent number: 8324737
    Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: December 4, 2012
    Assignee: Intel Corporation
    Inventors: Biju Chandran, Sandeep B Sane
  • Publication number: 20110156254
    Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.
    Type: Application
    Filed: March 7, 2011
    Publication date: June 30, 2011
    Inventors: Sandeep B. Sane, Biju Chandran
  • Patent number: 7901982
    Abstract: Embodiments of a method of attaching an integrated circuit (IC) die to a substrate are disclosed. In one embodiment, at a first temperature, a solder disposed between the IC die and substrate is reflowed. The reflowed solder is allowed to solidify to form electrical connections between the IC die and substrate. At a second temperature less than the first temperature, a liquid curable underfill material is placed in a gap between the IC die and substrate, and this underfill material may be placed in the gap, at least in part, by capillary action. The second temperature is maintained while curing the underfill material, and this second temperature is below a melting temperature of the solidified solder. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Sandeep B Sane, Biju Chandran
  • Publication number: 20090275175
    Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.
    Type: Application
    Filed: July 13, 2009
    Publication date: November 5, 2009
    Inventors: Sandeep B. Sane, Biju Chandran
  • Patent number: 7579213
    Abstract: A process for assembling a package for a semiconductor device is described. The process includes reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventors: Sandeep B Sane, Biju Chandran
  • Patent number: 7312527
    Abstract: A method, apparatus and system with a semiconductor package including a thermal interface material dam enclosing a volume of thermal interface material.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Sandeep B. Sane, Nitin Deshpande, Chia-Pin Chiu
  • Patent number: 7304391
    Abstract: A method of packaging a die includes reflowing the solder to electrically connect the die to a substrate at a first temperature, cooling the die and substrate to a second temperature, and placing a heated epoxy in contact with the die and the substrate. The method also includes holding the die and substrate at the second temperature for a time sufficient to allow the epoxy to cure, and cooling the die, substrate and epoxy. The second temperature is less than the first temperature. In addition, the die and substrate are not cooled to a temperature significantly below the second temperature until after the heated epoxy is placed in contact with the die and substrate.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: December 4, 2007
    Assignee: Intel Corporation
    Inventors: Sandeep B Sane, Biju Chandran
  • Patent number: 7166540
    Abstract: A method and apparatus for mounting semiconductor die and integral heat spreader are disclosed. In one embodiment, thermal expansion of the integral heat spreader is restricted by physical constraints during the process of heating interface material that bonds the integral heat spreader and semiconductor die together. In an alternative embodiment, thermal expansion of the integral hat spreader is restricted by applying an external compressive force to the integral heat spreader while heating interface material that bonds the integral heat spreader and semiconductor die together.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: January 23, 2007
    Assignee: Intel Corporation
    Inventors: Nitin A. Deshpande, Sandeep B. Sane
  • Patent number: 6919224
    Abstract: A method of packaging a die includes reflowing the solder to electrically connect the die to a substrate at a first temperature, cooling the die and substrate to a second temperature, and placing a heated epoxy in contact with the die and the substrate. The method also includes holding the die and substrate at the second temperature for a time sufficient to allow the epoxy to cure, and cooling the die, substrate and epoxy. The second temperature is less than the first temperature. In addition, the die and substrate are not cooled to a temperature significantly below the second temperature until after the heated epoxy is placed in contact with the die and substrate.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 19, 2005
    Assignee: Intel Corporation
    Inventors: Sandeep B Sane, Biju Chandran
  • Patent number: 6788859
    Abstract: A method and an article made by a method for embedding optical fibers into an organic laminate structure. The optical fiber cabling, along with its cladding, is placed upon a first laminate layer that includes a composite made of silica fillers and a frictionless material such as polytetrafluoroethylene (PTFE). Then a second layer of PTFE material with silica fillers and copper sheeting is placed on top of the PTFE with silica fillers composite. The PTFE material with silica fillers flows about the optical fibers at a temperature approximately fifty degrees above the PTFE with silica fillers material's melting point. This procedure completely encases the optical fibers within an opaque sheath.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: September 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Voya R. Markovich, Sandeep B. Sane, Sanjeev Sathe