Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract: Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.

Abstract: Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.

Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.

Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.

Abstract: Embodiments of a method of attaching an integrated circuit (IC) die to a substrate are disclosed. In one embodiment, at a first temperature, a solder disposed between the IC die and substrate is reflowed. The reflowed solder is allowed to solidify to form electrical connections between the IC die and substrate. At a second temperature less than the first temperature, a liquid curable underfill material is placed in a gap between the IC die and substrate, and this underfill material may be placed in the gap, at least in part, by capillary action. The second temperature is maintained while curing the underfill material, and this second temperature is below a melting temperature of the solidified solder. Other embodiments are described and claimed.

Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.

Abstract: A process for assembling a package for a semiconductor device is described. The process includes reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.