Abstract: Presented herein is a system and method for reducing the total size of the frame buffer portion of a decoding circuit. The reduction in size is possible because first portions of B-pictures are displayed while second portions occurring later in the raster order are decoded. The foregoing allows the second portions occurring later in the raster order to overwrite third portions of the picture that have already been displayed. As a result, the frame buffer for providing the frame from a decoder to the display engine need only store the portion that is being displayed and the portion that is being decoded.

Abstract: Systems and method for processing v-chip data for an MPEG-2 decoder with personal video recording functionality are provided. In one example, a system that processes V-Chip data with personal video recording functionality may include a data transport engine and a video decoder. The video decoder may be coupled to the data transport engine and may be adapted to parse out V-Chip data.

Abstract: Error concealment for motion picture expert group (MPEG) decoding with personal video recording functionality. Error concealment of MPEG data may take place within various components within playback, recording, reading and writing data systems. The error concealment may be provided within existing systems whose components may not be capable of accommodating errors within MPEG data. In certain embodiments, the available data that contain no errors is maximized to conceal those portions of the data that do include errors. Various layers may be accommodated while performing error concealment, including the MPEG transport stream layer, the video layer, and the audio layer.

Abstract: Presented herein is a system, method, and apparatus for audio and video synchronization. In one embodiment, there is presented a method for displaying audio data and video data. The method comprises examining a plurality of portions of the audio data, where each of said plurality of portions of audio data is associated with a time stamp; examining a plurality of portions of the video data, where each of said plurality of portions of the video data is associated with a time stamp; decoding one of the portions of the video data; and decoding one of the portions of the audio data while decoding the one of the portions of the video data. The difference between the time stamp associated with the one of the portions of the video data and the time stamp associated with the one of the portions of the audio data is within a certain margin of error from a predetermined offset.

Abstract: Systems and methods that provide personal video recording trick modes are provided. In one example, a method that provides a trick mode in a personal video recording system may include the steps of receiving a transport stream; storing data from the transport stream in a data storage; generating index table using the data from the transport stream; receiving a trick mode command; and accessing, based on the trick mode command, particular data in the data storage using the index table.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: A system and method that support display of video fields using related data encoded in data structures. Each data structure is associated with one video field and contains all the information associated with the display of the video field. The data structure is encoded with the video field that is displayed exactly one field prior to the field associated with the data structure. In an embodiment of the present invention, the data structure contains all the information associated with the display of a video field, regardless of whether certain data changes from one field to the next.

Abstract: A method and apparatus are provided for implementing an enhanced reduced memory mode (RMM) of decoding HDTV MPEG-2 video stream. In one instance, the RMM mode is adaptively enabled with up/down conversion by using the picture-type information. In another instance, the RMM mode is provided by performing anchor-frame compression/decompression by using adaptive DPCM technique with picture-type information. The quantization (PCM) tables are generated using the Lloyd algorithm. Further, the predictor for each pixel is determined by a use of the Graham rule.

Abstract: A video receiver comprising a single decoder may be operable to decode concurrently, by the single decoder, a plurality of received programs. The plurality of received programs may comprise a current program associated with a current channel and one or more other programs associated with one or more corresponding other channels. The video receiver may be operable to cause display of the decoded current program associated with the current channel for viewing. The plurality of received programs may be received via a single transport stream. The plurality of received programs may be received via a plurality of transport streams. The video receiver may be operable to switch from the current channel to one of the other channels based on a received request. The video receiver may be operable to cause display of one of the decoded other programs which is associated with the switched channel.

Abstract: In one embodiment of the invention, an apparatus for scan testing an integrated circuit is provided. The apparatus includes a combinational logic network; and a device for reducing gate switching in the combinational logic network to reduce power consumption during a scan test on the combinational logic network. The device for reducing gate switching in the combinational logic network includes a device for periodically isolating scan data from the combination logic network; and a device for periodically holding functional data coupled into the combinational network substantially steady. In one embodiment of the invention, the device for reducing gate switching in the combinational logic network is a plurality of serially coupled scan registers each having a pair of opposed controlled outputs with one controlled output providing scan output data and another controlled output providing functional data to the combinational logic network.

Abstract: Disclosed are various embodiments for displaying pictures at high speed. In one embodiment, a system includes a buffer for storing parameters associated with a predetermined number of the pictures during a video display period. The system further includes a video decoder for decoding particular ones of the predetermined number of the pictures. The predetermined ones are either reference pictures or pictures that are to be displayed at high speed. The pictures that are displayed in high speed at each display interval have a constant time-lapse between the pictures that are displayed in high speed at the next display interval.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: A system, method, and apparatus for reducing the video decoder processing requirements are presented herein. During a rewind operation, a reference picture for a group of pictures is decoded and stored into a reference frame buffer. By storing a reference picture for the group, the reference picture need not be decoded to display each picture in the group during the rewind operation.

Abstract: In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments. A decompressor circuit receives a decompressor input and is operatively connected to the scan-segment input ends, and a compressor circuit is operatively connected to the scan segment output ends and generates a compressor output. Isolation circuits at scan-segment exits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.

Abstract: A system, method, and apparatus for providing display parameters from the decode process to the display process are presented herein. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images as well as the parameters and stores each image in a separate image buffer. Additionally, the decode process stores the parameters which facilitate the display process in a buffer descriptor structure associated with the image buffer. The display process uses the parameters stored in the buffer descriptor structure during the display process.

Abstract: Presented herein are system(s), method(s), and apparatus for determining the presentation time for a picture without a presentation time stamp. A first and second picture are decoded. The first picture is a reference picture for the second picture. The presentation time for the second pictures is computed as a function of a presentation time and a decode time for the first picture.