Abstract: Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order.

Abstract: Presented herein is a direct memory access engine for providing data words in reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order. A set of multiplexers reverses the bit positions of the words in the local buffer.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: Described herein is a system and method for audio visual synchronization. The picture are displayed by receiving an identifier, said identifier associated with a frame buffer storing a picture; extracting a presentation time stamp associated with the picture, wherein the picture is associated with a time stamp; comparing a local time clock value to the presentation time stamp; determining that the picture is mature for presentation if the presentation time stamp exceeds the local time clock value by less than a first predetermined threshold; and determining that the picture is mature for presentation if the local time clock value exceeds the presentation time stamp by less than a second predetermined threshold.

Abstract: A system and method for displaying frames with dynamically changing display parameters is described herein. The display engine stores new display parameters detected by the decoder in one buffer of a ping pong buffer, while continuing to use another set of display parameters stored in the other ping pong buffer. The display engine switches the buffers when the first frame for which the new display parameters are applicable is to be presented.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: Presented herein are a system, method, and apparatus for improving scaling with early deinterlacing. Interlaced frames are deinterlaced prior to scaling. Accordingly, the scaler scales an entire frame, in contrast to individual fields, thereby resulting in an improved scaling function.

Abstract: Present herein is a low memory and MIPS efficient technique for decoding Huffman codes using multi-stage, multi-bits lookup at different levels. A binary tree is cut at levels depending on the quotient of the number of existing nodes and the number of possible nodes.

Abstract: Presented herein is a system, method, and apparatus for displaying a plurality of video sequences in real-time while reducing the required buffer memory. In an exemplary embodiment, a decoder system is presented that decodes and presents two video sequences, with three frame buffers per video sequence.

Abstract: Presented herein is a system and method for reducing the total size of the frame buffer portion of a decoding circuit. The reduction in size is possible because first portions of B-pictures are displayed while second portions occurring later in the raster order are decoded. The foregoing allows the second portions occurring later in the raster order to overwrite third portions of the picture that have already been displayed. As a result, the frame buffer for providing the frame from a decoder to the display engine need only store the portion that is being displayed and the portion that is being decoded.

Abstract: A system, method, and apparatus for playback of multiple video elementary streams is presented herein. A host processor modifies the video elementary streams to allow a transport demultiplexer to distinguish among the plurality of the video elementary streams.

Abstract: Presented herein is a scheme for processing multilayered packets. In one embodiment, an application engine aligns a lower level packet header with data objects in the multilayered packet. Additionally, the memory stores the objects of the multilayered packet, such that the objects start at the beginning of a data word. Remainder portions of data words can store 0's. Additionally, an object table stores records comprising object identifiers associated with particular objects, and the address where the particular object is stored.

Abstract: Disclosed herein are system(s), method(s), and apparatus for simultaneously displaying multiple video streams. The video streams are encoded as a video sequence, which can include temporally coded bi-directional pictures. A decoder decodes a picture from each of the video sequences, which can include temporally coded bi-directional pictures. The set of frame buffers stores the past prediction frames and the future prediction frames for each video sequence. A table indicates the location of the past prediction frame and the future prediction frame for each video sequence. A display engine prepares a frame from each video sequence for display. The location of the frames for display are indicated by a register.

Abstract: Presented herein are a system, method, and apparatus for decoupling the video decoder and display engine. Parameter buffers and a queue indicate display parameters and display order for the display engine to appropriately present the frame for display.

Abstract: Presented herein are a system, method, and apparatus for retrieving an object from memory. The object can be stored in a manner, such that the first byte of the object and the last byte of the object are in the middle of the memory data words. The object is retrieved by a direct memory access controller. The direct memory access controller, when provided with a read transaction with the starting address and the ending address of the object, retrieves the data words storing the object, and overwrites the portions of the data word that precede and follow the object.

Abstract: A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.

Abstract: A system and method for detecting packetized elementary stream (PES) packet headers is presented herein. PES packet headers are detected by a combination of hardware and firmware. Hardware logic is used to detect the PES start codes while multithreaded firmware us used to process the packet.

Abstract: A system and method for detecting PES headers is presented herein. PES headers are detected by a combination of hardware and firmware. Hardware logic is used to detect the PES start codes while multithreaded firmware us used to process the packet.

Abstract: Presented herein are systems and methods for two address map for transactions between an X-bit processor and a Y-bit wide memory. A processor subsystem comprises a first address space, a second address space, and a bridge. The first address space stores data words of a first length. The second address space stores data words of a second length. The bridge performs one transaction after receiving a transaction with an address corresponding to the first address space and performs two transactions after receiving a transaction with the address corresponding to the second address space.