Patents by Inventor Sandeep Jain
Sandeep Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12265124Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N?1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N?1 number of redundant flip-flops is observed through the functional path to determine faults.Type: GrantFiled: September 26, 2023Date of Patent: April 1, 2025Assignee: STMicroelectronics International N.V.Inventors: Sandeep Jain, Akshay Kumar Jain, Jeena Mary George
-
Patent number: 12265121Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.Type: GrantFiled: May 23, 2023Date of Patent: April 1, 2025Assignee: STMicroelectronics International N.V.Inventors: Sandeep Jain, Shalini Pathak, Prateek Singh
-
Publication number: 20250102574Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N-1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N-1 number of redundant flip-flops is observed through the functional path to determine faults.Type: ApplicationFiled: September 26, 2023Publication date: March 27, 2025Inventors: Sandeep Jain, Akshay Kumar Jain, Jeena Mary George
-
Publication number: 20250067803Abstract: According to an embodiment, a first aspect relates to a method for testing a scan chain. The method includes segmenting the scan chain into two or more segments; adding a respective multiplexer at end points of each segment, wherein each pair of sequential segment shares a common multiplexer in between; asserting a select signal at a select terminal of the multiplexers such that a relative position of the two or more segments is rearranged positionally in a rearranged scan chain; generating a test pattern to be communicated to an input terminal of the rearranged scan chain and observing a test result at an output of the rearranged scan chain; and determining a fault condition in the rearranged scan chain based on comparing the test result and an expected result.Type: ApplicationFiled: August 21, 2023Publication date: February 27, 2025Inventors: Sandeep Jain, Shalini Pathak
-
Patent number: 12208354Abstract: The present invention concerns a method of decarbonating a gas stream containing from 15% to 60% carbon dioxide, by passage of the said gas stream over a zeolitic agglomerate comprising at least one binder and at at least one zeolite, and having a mesoporous volume of between 0.02 cm3·g?1 and 0.15 cm3·g?1 and a mesoporous volume fraction of between 0.1 and 0.5, preferably between 0.15 and 0.45.Type: GrantFiled: March 14, 2019Date of Patent: January 28, 2025Assignee: Arkema FranceInventors: Sandeep Jain, Leonel Gomes, Alexandre Terrigeol
-
Publication number: 20250027994Abstract: An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.Type: ApplicationFiled: July 17, 2023Publication date: January 23, 2025Applicant: STMicroelectronics International N.V.Inventors: Sandeep JAIN, Shalini PATHAK, Pooja JAIN
-
Patent number: 12203985Abstract: An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.Type: GrantFiled: July 17, 2023Date of Patent: January 21, 2025Assignee: STMicroelectronics International N.V.Inventors: Sandeep Jain, Shalini Pathak, Pooja Jain
-
Publication number: 20240393393Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.Type: ApplicationFiled: May 23, 2023Publication date: November 28, 2024Inventors: Sandeep Jain, Shalini Pathak, Prateek Singh
-
Publication number: 20240385241Abstract: Test circuitry includes a scan-compressor receiving n scan-input bits from n input-pins and compressing those bits for distribution among z scan-chains, z being less than n. A scan-decompressor receives test response data from the scan-chains and decompresses the test response data, reconstructing n scan-output bits. An OCC generates a test-clock based on clock-bits received from a clock-chain, with the test-clock operating the scan-chains and the clock-chain. The clock-chain receives m clock-chain input bits from m of the input-pins, m being less than n, and provides the clock-bits to the OCC for generating the test-clock. The test circuitry performs tests on the IC. Each test is associated with the test-clock generated by the OCC based on a given set of clock-bits. Tests associated with the test-clock generated by the OCC based on the same given set of clock-bits are performed after a single loading of that same given set of clock-bits.Type: ApplicationFiled: May 18, 2023Publication date: November 21, 2024Applicant: STMicroelectronics International N.V.Inventors: Sandeep JAIN, Pooja JAIN, Esha PAL
-
Patent number: 12111798Abstract: Embodiments map a source schema to a target schema using a feature store. Embodiments receive a file including a plurality of source schema elements and a plurality of target schema elements, the file including a plurality of unmapped elements. Embodiments retrieve rule based mappings for the unmapped elements between the source schema elements and the target schema elements. Based on semantic matching of the source schema elements, embodiments retrieve feature store based mappings from the feature store for the unmapped elements between the source schema elements and the target schema elements. Embodiments then generate one or more similarity scores for mappings of the source schema elements to the target schema elements.Type: GrantFiled: January 28, 2022Date of Patent: October 8, 2024Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Yagnesh Dilipbhai Kotecha, Hari Bhaskar Sankaranarayanan, Sandeep Jain, Jagathi Harshitha Arumalla
-
Patent number: 12105145Abstract: A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.Type: GrantFiled: July 31, 2023Date of Patent: October 1, 2024Assignee: STMicroelectronics International N.V.Inventors: Sandeep Jain, Shalini Pathak
-
Publication number: 20240248791Abstract: This application relates to apparatus and methods for the monitoring of nodes within datacenters. In some examples, a computing device, such as a node, receives a monitoring file from a monitoring server, where the monitoring file includes a plurality of node health checks. The computing device is configured to execute the monitoring file based on a type of the computing device. Further, and based on the execution of the monitoring file, the computing device is configured to determine that at least one of the plurality of node health checks failed. In response to determining that the at least one of the plurality of node health checks failed, the computing device is configured to generate an alert message identifying the node health checks that failed. Further, the computing device is configured to transmit the alert message to the monitoring server for display.Type: ApplicationFiled: March 18, 2024Publication date: July 25, 2024Inventors: Swapna Kumar Biswal, Narendran Somasundaram, Saurabh Sandeep Jain, Shriniwas Phalke, Satheesh Kumar Ulaganathan
-
Publication number: 20240228211Abstract: A cooler for storing and dispensing products is disclosed. The cooler includes a housing having an open access. A first glider and a second glider are disposed on a shelf interior of the housing, with a front end closer to the open access and a back end. The first and second gliders each has a partition and a pushing mechanism. The partition can prevent a user from reaching the products on both the first and second gliders at the same time with a single hand. The pushing mechanism can be adjustable between a locked condition to inhibit a movement of the products from the front end to the back end and a released condition to allow a movement of the products from the front end to the back end.Type: ApplicationFiled: October 19, 2023Publication date: July 11, 2024Inventor: Sandeep JAIN
-
Publication number: 20240132316Abstract: A cooler for storing and dispensing products is disclosed. The cooler includes a housing having an open access. A first glider and a second glider are disposed on a shelf interior of the housing, with a front end closer to the open access and a back end. The first and second gliders each has a partition and a pushing mechanism. The partition can prevent a user from reaching the products on both the first and second gliders at the same time with a single hand. The pushing mechanism can be adjustable between a locked condition to inhibit a movement of the products from the front end to the back end and a released condition to allow a movement of the products from the front end to the back end.Type: ApplicationFiled: October 18, 2023Publication date: April 25, 2024Inventor: Sandeep JAIN
-
Patent number: 11966280Abstract: This application relates to apparatus and methods for the monitoring of nodes within datacenters. In some examples, a computing device, such as a node, receives a monitoring file from a monitoring server, where the monitoring file includes a plurality of node health checks. The computing device is configured to execute the monitoring file based on a type of the computing device. Further, and based on the execution of the monitoring file, the computing device is configured to determine that at least one of the plurality of node health checks failed. In response to determining that the at least one of the plurality of node health checks failed, the computing device is configured to generate an alert message identifying the node health checks that failed. Further, the computing device is configured to transmit the alert message to the monitoring server for display.Type: GrantFiled: March 17, 2022Date of Patent: April 23, 2024Assignee: Walmart Apollo, LLCInventors: Swapna Kumar Biswal, Narendran Somasundaram, Saurabh Sandeep Jain, Shriniwas Phalke, Satheesh Kumar Ulaganathan
-
Publication number: 20240122858Abstract: Modified-release pharmaceutical compositions of ruxolitinib or a pharmaceutically acceptable salt thereof are disclosed. Preferably, the invention relates to oral modified-release pharmaceutical compositions of ruxolitinib, which enable once-daily administration. Oral modified-release compositions of ruxolitinib, methods for their administration, processes for their preparation, and use of these compositions for treatment of diseases treatable by ruxolitinib are also described.Type: ApplicationFiled: December 7, 2023Publication date: April 18, 2024Applicant: SLAYBACK PHARMA LLCInventors: Paras P. JAIN, Krishna Mohan LAKSHMIPATHULA, Somnath Devidas NAVGIRE, Hanimi Reddy BAPATU, Sandeep JAIN, Sumitra Ashokkumar PILLAI, Praveen Kumar SUBBAPPA
-
Publication number: 20240119779Abstract: A vending machine includes a housing defining a product compartment and a front wall having a transparent portion. A platform is arranged within the product compartment of the vending machine for storing a product thereon, and the platform includes a first end opposite a second end. The vending machine further includes a product release mechanism that includes a gate arranged on the platform and movable from a closed position to an open position to release the product from the platform. A delivery bin having an open front end is arranged below the platform such that when the first gate is moved to the open position, the product falls under a force of gravity from the platform into the delivery bin for access by a consumer.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Gurmeet Singh BHUTANI, Sandeep JAIN
-
Publication number: 20240078108Abstract: A processor-implemented method and a system for artifact order and rank synchronization is provided. The method includes determining, using a ranking module, if a rank of an artifact has changed across disparate tools in an organization eco-system of a source comprising an end system from where integration reads the data for synchronization, by determining if hierarchy processing is required or not. The method also includes updating, using a rank update module, the rank of the artifact in a target comprising an end system where integration writes data.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: SANDEEP JAIN, Gaurav Chavda
-
Patent number: 11900756Abstract: A vending machine includes a housing defining a product compartment and a front wall having a transparent portion. A platform is arranged within the product compartment of the vending machine for storing a product thereon, and the platform includes a first end opposite a second end. The vending machine further includes a product release mechanism that includes a gate arranged on the platform and movable from a closed position to an open position to release the product from the platform. A delivery bin having an open front end is arranged below the platform such that when the first gate is moved to the open position, the product falls under a force of gravity from the platform into the delivery bin for access by a consumer.Type: GrantFiled: January 20, 2022Date of Patent: February 13, 2024Assignee: PepsiCo, Inc.Inventors: Gurmeet Singh Bhutani, Sandeep Jain
-
Publication number: 20240009188Abstract: Amorphous solid dispersions of nilotinib fumarate or nilotinib tartrate are provided, as well as pharmaceutical compositions thereof, wherein the compositions exhibit enhanced bioavailability in the fasted state. Preferably, the compositions may be orally administered to a patient in either the fed or fasted state, with a decrease or elimination of the food effect. Preferably, following oral administration of the pharmaceutical compositions, there is no substantial difference in the pharmacokinetic parameters (e.g., Cmax, AUC0-t and/or AUC0-infinity) of nilotinib, regardless of whether the pharmaceutical compositions are administered to a subject in the fed or fasted state.Type: ApplicationFiled: September 15, 2023Publication date: January 11, 2024Applicant: SLAYBACK PHARMA LLCInventors: Paras P. JAIN, Ajay Kumar SINGH, Keerthi PRIYA, Girish Kumar JAIN, Girish G. KORE, Sandeep JAIN, Hanimi Reddy BAPATU