Patents by Inventor Sandeep K. Guliani
Sandeep K. Guliani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220284948Abstract: Column read enabled three dimensional cross-point memory is optimized to reduce delay time due to partition busy times incurred when reading from a same partition. A column read enabled memory media stores each entry of a logical column of an array of bits in contiguous different physical rows and different physical columns of the cross-point memory array than any other entry of the logical column. Subsets of the contiguous different physical rows are stored in different partitions to reduce the delay time incurred when performing column reads from a same partition to improve media management operation performance.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Inventors: Sourabh DONGAONKAR, Chetan CHAUHAN, Jawad B. KHAN, Rajesh SUNDARAM, Sandeep K. GULIANI
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Publication number: 20210407564Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.Type: ApplicationFiled: September 7, 2021Publication date: December 30, 2021Inventors: Sourabh DONGAONKAR, Chetan CHAUHAN, Jawad B. KHAN, Sandeep K. GULIANI, William K. WALLER
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Patent number: 11114143Abstract: A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.Type: GrantFiled: February 22, 2019Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Balaji Srinivasan, Sandeep K. Guliani, DerChang Kau, Ashir G. Shah
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Publication number: 20200273508Abstract: A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.Type: ApplicationFiled: February 22, 2019Publication date: August 27, 2020Inventors: Balaji SRINIVASAN, Sandeep K. GULIANI, DerChang KAU, Ashir G. SHAH
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Patent number: 10546634Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: GrantFiled: September 24, 2018Date of Patent: January 28, 2020Assignee: Intel CorporationInventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
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Patent number: 10497434Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: GrantFiled: August 20, 2018Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal
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Publication number: 20190096482Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: ApplicationFiled: September 24, 2018Publication date: March 28, 2019Inventors: Raymond W. ZENG, Mase J. TAUB, Kiran PANGAL, Sandeep K. GULIANI
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Publication number: 20190074058Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: ApplicationFiled: August 20, 2018Publication date: March 7, 2019Inventors: Mase J. TAUB, Sandeep K. GULIANI, Kiran PANGAL
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Patent number: 10134468Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: GrantFiled: March 21, 2017Date of Patent: November 20, 2018Assignee: Intel CorporationInventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
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Patent number: 10056136Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: GrantFiled: June 5, 2017Date of Patent: August 21, 2018Assignee: Intel CorporationInventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal
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Patent number: 9792986Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.Type: GrantFiled: May 29, 2015Date of Patent: October 17, 2017Assignee: INTEL CORPORATIONInventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal, Raymond W. Zeng
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Publication number: 20170294228Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: ApplicationFiled: June 5, 2017Publication date: October 12, 2017Inventors: Mase J. TAUB, Sandeep K. GULIANI, Kiran PANGAL
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Publication number: 20170229172Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: ApplicationFiled: March 21, 2017Publication date: August 10, 2017Applicant: Intel CorporationInventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI
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Patent number: 9715930Abstract: Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory (NVRAM), such as a phase change memory (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device; a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device; and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.Type: GrantFiled: June 4, 2015Date of Patent: July 25, 2017Assignee: Intel CorporationInventors: Sandeep K. Guliani, Ved Pragyan
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Patent number: 9685204Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: GrantFiled: June 22, 2016Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
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Patent number: 9601193Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: GrantFiled: September 14, 2015Date of Patent: March 21, 2017Assignee: INTEL CORPORATIONInventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
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Publication number: 20170076794Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Applicant: INTEL CORPORATIONInventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI
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Patent number: 9543005Abstract: A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.Type: GrantFiled: September 7, 2015Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Sandeep K Guliani, Kiran Pangal, Balaji Srinivasan, Chaohong Hu
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Publication number: 20160358652Abstract: Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory (NVRAM), such as a phase change memory (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device; a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device; and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 4, 2015Publication date: December 8, 2016Inventors: Sandeep K. Guliani, Ved Pragyan
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Publication number: 20160351258Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.Type: ApplicationFiled: May 29, 2015Publication date: December 1, 2016Applicant: Intel CorporationInventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal, Raymond W. Zeng