Abstract: A programmable logic device that includes a voltage input and a detection circuit coupled to the voltage input is described. The detection circuit detects whether a voltage applied to the voltage input exceeds a predetermined value. The programmable logic device also includes a configuration circuit coupled to the detection circuit. The configuration circuit configures the programmable logic device to receive a current sufficient for program and erase operations through the voltage input in response to the detection circuit detecting that the voltage exceeds the predetermined value.

Abstract: A bias circuit for a memory cell having first and second floating gate devices, and third and fourth reference devices, one of which has an output terminal coupled thereto is described. In one embodiment, the bias circuit includes a first capacitor including a first terminal coupled to the gates of the first and second devices, and a second terminal coupled to a power supply terminal, and a second capacitor including a first terminal coupled to the gates of the third and fourth devices, and a second terminal coupled to the power supply terminal. The bias circuit further includes a reference circuit including a first terminal having a first signal thereon and coupled to the gates of the first and second devices, and a second terminal having a second signal thereon and coupled to the gates of the third and fourth devices, the reference circuit to periodically turn on the first and second signals. The bias circuit reduces standby current and wake up time of redundant circuits in non-volatile memory devices.

Abstract: Two parallel valid data detectors are provided to detect whether a sinusoidal electrical signal from a twisted pair medium represents valid data. One handles phase 0 degree starting sinusoidal electrical signal, the other handle phase 180 degree. In either case, the valid data detectors receive two series of pulses as input, indicating positive and negative differences respectively between RD and RD from the twisted pair medium. In response, if the valid data detector detects the proper data pattern within a predetermined time frame, it outputs a signal indicating the detection of valid data. The "phase 0" valid data detector looks for a high to low and back to high data pattern, whereas, the "phase 180" valid data detector looks for a low to high and back to low data pattern.

Abstract: A circuit is described as a generating supply-independent voltage reference. In MOS technology, a current mirror section incorporating a pair of N-channel and W-channel tracking devices are coupled to a power supply V.sub.cc for generating a voltage reference output that is directly proportional to V.sub.tn -V.sub.tw. V.sub.tn is the gate threshold voltage of the N-channel device, while V.sub.tw is the gate threshold voltage of W-channel device. A start-up circuit is further coupled to the power supply V.sub.cc and to the current mirror section for maintaining the operating point V.sub.1 of the circuit that is independent of supply voltage. The degree of supply independence can be further increased by adding a pair of P-channel device to the output of the present invention. Thus, the present invention generates a voltage reference that is independent from power supply, temperature and process while minimizing power dissipation.