Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

Abstract: A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

Abstract: A method and apparatus to segment a programmable non-volatile memory array into at least two banks. The banks include memory cells. Each bank in the at least two banks is provided with a local programming voltage. Each local programming voltage is independent of the other local programming voltages supplied to the other banks.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: The present invention provides a method, apparatus, and system for rapid transition of a charge pump circuit from a low power state to a high power state. The charge pump circuit has at least one pump stage. The at least one pump stage includes at least a first capacitor coupled to a gate of a first switching transistor forming a boot node and at least a second capacitor coupled to an output node of the at least one pump stage. It is determined whether the charge pump circuit is in the low power state or the high power state. If the charge pump circuit is in the low power state, a first predetermined voltage and a second predetermined voltage that are different than the ground voltage level are applied to the boot node and the output node, respectively. If the charge pump circuit is in the high power state, the first predetermined voltage and the second predetermined voltage are removed from the boot node and the output node, respectively.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A method and apparatus for controlling use of an electronic system is described. Use of the electronic system is controlled by programming at least one unique code into an auxiliary memory of the electronic system. The auxiliary memory is a permanently lockable memory that is located outside of a main memory array space. The unique code is compared to at least one component code. Use of the electronic system is controlled based on a predefined relationship between the unique code and the component code.

Abstract: A method for generating a positive temperature correlated clock frequency is described. The method comprises conducting current through a resistor to charge a capacitor. When the capacitor is charged to a trip point of the inverter at the input of the inverter chain, a transition in an output signal of an inverter chain is triggered. The capacitor is discharged through a grounding device when the output signal activates said grounding device.