Patents by Inventor Sandeep Kumar Goel

Sandeep Kumar Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985922
    Abstract: A device includes a first memory circuit, a second memory circuit and a processing circuit. The memory circuit is configured to store a distinguishable identification (ID). The second memory circuit is configured to store first hash data, wherein the first hash data is generated according to the distinguishable ID. The processing circuit is configured to generate second hash data according to the distinguishable ID when the device is powered on, and to compare the first hash data and the second hash data to determine whether the second hash data matches the first hash data.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Haohua Zhou, Sandeep Kumar Goel
  • Publication number: 20210089696
    Abstract: A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group and/or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing the slow operation group operation on the machine learning hardware configuration, finalizing the machine learning hardware configuration capable of successfully executing least one test data set.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Inventors: Kai-Yuan TING, Sandeep Kumar GOEL, Tze-Chiang HUANG, Yun-Han LEE
  • Publication number: 20200410144
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yuan TING, Sandeep Kumar GOEL, Yun-Han LEE, Mei WONG, Hsin-Cheng CHEN
  • Patent number: 10871518
    Abstract: Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee, Ankita Patidar
  • Patent number: 10867098
    Abstract: A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing operations of the slow operation group on the initial machine learning hardware configuration, modifying the initial machine learning hardware configuration in response to a determination that the slow group operation fails to produce an expected result in response to at least one set of inputs; and executing a fast group operation using a machine learning software code.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Yuan Ting, Sandeep Kumar Goel, Tze-Chiang Huang, Yun-Han Lee
  • Patent number: 10867089
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation of various loads on one or more batteries of an electronic device resulting from the electronic device performing one or more functional behaviors. Before this electronic simulation occurs, the electronic device is modeled using the high-level software language or the high-level software format. For example, a battery discharge model, a regulator efficiency model, a power delivery network (PDN) model, or a component power model are used to model behaviors of the one or more batteries, regulator circuitry, power delivery network (PDN) circuitry, and other electronic circuits, respectively, of the electronic device.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Charlie Zhou, Kai-Yuan Ting, Sandeep Kumar Goel, Tze-Chiang Huang, Yun-Han Lee
  • Publication number: 20200379013
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Publication number: 20200372124
    Abstract: A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing operations of the slow operation group on the initial machine learning hardware configuration, modifying the initial machine learning hardware configuration in response to a determination that the slow group operation fails to produce an expected result in response to at least one set of inputs; and executing a fast group operation using a machine learning software code.
    Type: Application
    Filed: September 25, 2019
    Publication date: November 26, 2020
    Inventors: Kai-Yuan TING, Sandeep Kumar GOEL, Tze-Chiang HUANG, Yun-Han LEE
  • Publication number: 20200311329
    Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
  • Publication number: 20200304133
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Sandeep Kumar GOEL, Ji-Jan CHEN, Stanley JOHN, Yun-Han LEE, Yen-Hao HUANG
  • Patent number: 10782318
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Patent number: 10776538
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yuan Ting, Sandeep Kumar Goel, Yun-Han Lee, Mei Wong, Hsin-Cheng Chen
  • Publication number: 20200280527
    Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 3, 2020
    Inventors: RAVI VENUGOPALAN, SANDEEP KUMAR GOEL, YUN-HAN LEE
  • Patent number: 10719648
    Abstract: A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tze-Chiang Huang, Kai-Yuan Ting, Sandeep Kumar Goel, Yun-Han Lee, Shereef Shehata, Mei Wong
  • Patent number: 10685157
    Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
  • Patent number: 10680627
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Patent number: 10666578
    Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ravi Venugopalan, Sandeep Kumar Goel, Yun-Han Lee
  • Publication number: 20200124668
    Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 23, 2020
    Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Saman M.I ADHAM, Marat GERSHOIG
  • Publication number: 20200072901
    Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.
    Type: Application
    Filed: August 20, 2019
    Publication date: March 5, 2020
    Inventors: Sandeep Kumar Goel, Ankita Patidar
  • Publication number: 20200036879
    Abstract: An apparatus includes an image sensor having a light sensing region, the light sensing region being partitioned into a plurality of sub-regions, a first sub-region of the plurality of sub-regions has a first size, a second sub-region of the plurality of sub-regions has a second size different from the first size, and the second sub-region partially overlaps with the first sub-region. The apparatus further includes a processor coupled with the image sensor, wherein the processor includes a plurality of pixel processing units, and each processing unit of the plurality of processing units is configured to generate a processed image based on an image captured by a corresponding sub-region of the plurality of sub-regions. The apparatus further includes a plurality of lenses configured to focus incident light onto the image sensor.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Ashok MEHTA