Patents by Inventor Sandeep Kumar Goel
Sandeep Kumar Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220237353Abstract: Disclosed herein are related to a method, a device, and a non-transitory computer readable medium for testing a circuit model in an integrated circuit. In one aspect, to each of a plurality of sets of input conditions of a circuit model, a corresponding virtual defect is assigned. The virtual defect may be generated irrespective of a physical characteristic of an integrated circuit formed according to the circuit model. Each virtual defect may be associated with a corresponding set of input conditions. In one aspect, a table of the circuit model including a plurality of logic behavioral models of the circuit model is generated. Each of the plurality of logic behavioral models may include a corresponding set of the plurality of sets of input conditions, a corresponding output result, and the corresponding virtual defect. Based at least in part on the table of the circuit model, a test pattern for the circuit model can be generated.Type: ApplicationFiled: January 27, 2021Publication date: July 28, 2022Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yue Tian, Sandeep Kumar Goel
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Publication number: 20220230699Abstract: A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.Type: ApplicationFiled: April 5, 2022Publication date: July 21, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ankita Patidar, Sandeep Kumar Goel
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Patent number: 11386253Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.Type: GrantFiled: June 15, 2020Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
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Patent number: 11379643Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a dominant feature among a plurality of features of the plurality of paths. The dominant features of the plurality of groups are different from each other. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.Type: GrantFiled: December 15, 2020Date of Patent: July 5, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY, LIMITEDInventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
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Patent number: 11354465Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.Type: GrantFiled: September 14, 2020Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Yuan Ting, Sandeep Kumar Goel, Yun-Han Lee, Mei Wong, Hsin-Cheng Chen
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Patent number: 11343433Abstract: An apparatus includes an image sensor having a light sensing region, the light sensing region being partitioned into a plurality of sub-regions, a first sub-region of the plurality of sub-regions has a first size, a second sub-region of the plurality of sub-regions has a second size different from the first size, and the second sub-region partially overlaps with the first sub-region. The apparatus further includes a processor coupled with the image sensor, wherein the processor includes a plurality of pixel processing units, and each processing unit of the plurality of processing units is configured to generate a processed image based on an image captured by a corresponding sub-region of the plurality of sub-regions. The apparatus further includes a plurality of lenses configured to focus incident light onto the image sensor.Type: GrantFiled: October 7, 2019Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sandeep Kumar Goel, Yun-Han Lee, Ashok Mehta
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Publication number: 20220138385Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a dominant feature among a plurality of features of the plurality of paths. The dominant features of the plurality of groups are different from each other. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.Type: ApplicationFiled: December 15, 2020Publication date: May 5, 2022Inventors: Ankita PATIDAR, Sandeep Kumar GOEL, Yun-Han LEE
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Patent number: 11295831Abstract: A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.Type: GrantFiled: June 25, 2020Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Ankita Patidar, Sandeep Kumar Goel
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Patent number: 11231767Abstract: A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.Type: GrantFiled: August 24, 2018Date of Patent: January 25, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Yuan Ting, Ashok Mehta, Stanley John, Sandeep Kumar Goel
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Publication number: 20210407614Abstract: A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Inventors: Ankita Patidar, Sandeep Kumar Goel
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Publication number: 20210350055Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.Type: ApplicationFiled: July 19, 2021Publication date: November 11, 2021Inventors: Sandeep Kumar Goel, Ankita Patidar
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Patent number: 11163351Abstract: A device for power estimation is disclosed. The device includes a transformer circuit coupled with a processing circuit and a transaction interface. The transformer circuit is configured to count performance activities executed in the processing circuit and to compare count values of the performance activities with a predetermined value to determine a power state of the processing circuit. The transaction interface is configured to receive a request from the processing circuit and record a first timestamp, and further configured to receive a response from a memory model and record a second timestamp, the transaction interface being further configured to record a time difference between the first timestamp and the second timestamp as a time difference. The transformer circuit is further configured to determine the power state of the processing circuit based on both of the count values and the time difference.Type: GrantFiled: July 8, 2019Date of Patent: November 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Yuan Ting, Shereef Shehata, Tze-Chiang Huang, Sandeep Kumar Goel, Mei Wong, Yun-Han Lee
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Publication number: 20210326502Abstract: A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.Type: ApplicationFiled: July 1, 2021Publication date: October 21, 2021Inventors: Sandeep Kumar GOEL, Ankita PATIDAR, Yun-Han LEE
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Publication number: 20210281268Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.Type: ApplicationFiled: May 26, 2021Publication date: September 9, 2021Inventors: Sandeep Kumar GOEL, Ji-Jan CHEN, Stanley JOHN, Yun-Han LEE, Yen-Hao HUANG
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Patent number: 11113444Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of electronic circuitry for an electronic device. The electronic device includes scan flip-flops to autonomously test the electronic circuitry for various manufacturing faults. The EDA of the present disclosure statistically groups the scan flip-flops into scan chains in such a manner such that scan flip-flops within each scan chain share similar characteristics, parameters, or attributes. Thereafter, the EDA of the present disclosure intelligently arranges ordering for the scan flip-flops within each of the scan chains to optimize power, performance, and/or area of the electronic circuitry.Type: GrantFiled: October 29, 2018Date of Patent: September 7, 2021Inventors: Sandeep Kumar Goel, Yun-Han Lee, Vinay Kotha, Ankita Patidar
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Patent number: 11068633Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.Type: GrantFiled: August 20, 2019Date of Patent: July 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sandeep Kumar Goel, Ankita Patidar
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Publication number: 20210218577Abstract: A device includes a first memory circuit and a processing circuit. The first memory circuit is configured to store first hash data. The processing circuit is coupled to the first memory circuit. The processing circuit is configured to: at least based on a volume of the device, define a size of a distinguishable identification (ID) and a size of second hash data; based on a combination of at least one bit of each of the distinguishable ID and IDs of the device, generate the second hash data; and compare the first hash data with the second hash data, in order to identify whether the device is tampered. A method is also discloses herein.Type: ApplicationFiled: March 25, 2021Publication date: July 15, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Haohua ZHOU, Sandeep Kumar GOEL
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Patent number: 11055455Abstract: A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.Type: GrantFiled: February 12, 2020Date of Patent: July 6, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TSMC NANJING COMPANY, LIMITEDInventors: Sandeep Kumar Goel, Yun-Han Lee, Ankita Patidar
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Publication number: 20210192112Abstract: A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.Type: ApplicationFiled: February 12, 2020Publication date: June 24, 2021Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Ankita PATIDAR
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Patent number: 11025261Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.Type: GrantFiled: June 5, 2020Date of Patent: June 1, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang